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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 */
20
21#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022
Sean Nelson6b11ad22009-12-23 17:05:59 +000023/* FIMXE: Use erase_sector_jedec if not? */
Sean Nelson72a9a022009-12-22 22:15:33 +000024int erase_sector_29f040b(struct flashchip *flash, unsigned int address, unsigned int blocklen)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000025{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000026 chipaddr bios = flash->virtual_memory;
27
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000028 chip_writeb(0xAA, bios + 0x555);
29 chip_writeb(0x55, bios + 0x2AA);
30 chip_writeb(0x80, bios + 0x555);
31 chip_writeb(0xAA, bios + 0x555);
32 chip_writeb(0x55, bios + 0x2AA);
33 chip_writeb(0x30, bios + address);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000034
Sean Nelson6b11ad22009-12-23 17:05:59 +000035 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000036
37 /* wait for Toggle bit ready */
38 toggle_ready_jedec(bios + address);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000039
Sean Nelson72a9a022009-12-22 22:15:33 +000040 if (check_erased_range(flash, address, blocklen)) {
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000041 fprintf(stderr, "ERASE FAILED!\n");
42 return -1;
43 }
Uwe Hermannffec5f32007-08-23 16:08:21 +000044 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000045}
46
Sean Nelson72a9a022009-12-22 22:15:33 +000047/* erase chip with block_erase() prototype */
48int erase_chip_29f040b(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
49{
50 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
51 fprintf(stderr, "%s called with incorrect arguments\n",
52 __func__);
53 return -1;
54 }
55 return erase_29f040b(flash);
56}
57
Michael Karcher1c296ca2009-11-27 17:49:42 +000058/* FIXME: use write_sector_jedec? */
Uwe Hermann09e04f72009-05-16 22:36:00 +000059static int write_sector_29f040b(chipaddr bios, uint8_t *src, chipaddr dst,
60 unsigned int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000061{
62 int i;
63
64 for (i = 0; i < page_size; i++) {
Uwe Hermann0b7afe62007-04-01 19:44:21 +000065 if ((i & 0xfff) == 0xfff)
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000066 printf("0x%08lx", dst - bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +000067
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000068 chip_writeb(0xAA, bios + 0x555);
69 chip_writeb(0x55, bios + 0x2AA);
70 chip_writeb(0xA0, bios + 0x555);
71 chip_writeb(*src++, dst++);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000072
73 /* wait for Toggle bit ready */
74 toggle_ready_jedec(bios);
75
Uwe Hermann0b7afe62007-04-01 19:44:21 +000076 if ((i & 0xfff) == 0xfff)
Stefan Reinauer99349a52006-03-16 16:46:19 +000077 printf("\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000078 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000079
Uwe Hermannffec5f32007-08-23 16:08:21 +000080 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000081}
82
Ollie Lho761bf1b2004-03-20 16:46:10 +000083int probe_29f040b(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000084{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000085 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000086 uint8_t id1, id2;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000087
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000088 chip_writeb(0xAA, bios + 0x555);
89 chip_writeb(0x55, bios + 0x2AA);
90 chip_writeb(0x90, bios + 0x555);
Ollie Lho761bf1b2004-03-20 16:46:10 +000091
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000092 id1 = chip_readb(bios);
93 id2 = chip_readb(bios + 0x01);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000094
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000095 chip_writeb(0xF0, bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000096
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000097 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +000098
Uwe Hermann04aa59a2009-09-02 22:09:00 +000099 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000100 if (id1 == flash->manufacture_id && id2 == flash->model_id)
101 return 1;
102
103 return 0;
104}
105
Michael Karcher1c296ca2009-11-27 17:49:42 +0000106/* FIXME: use erase_chip_jedec? */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000107int erase_29f040b(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000108{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000109 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000110 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000111
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000112 chip_writeb(0xAA, bios + 0x555);
113 chip_writeb(0x55, bios + 0x2AA);
114 chip_writeb(0x80, bios + 0x555);
115 chip_writeb(0xAA, bios + 0x555);
116 chip_writeb(0x55, bios + 0x2AA);
117 chip_writeb(0x10, bios + 0x555);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000118
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000119 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000120 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000121
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000122 if (check_erased_range(flash, 0, total_size)) {
123 fprintf(stderr, "ERASE FAILED!\n");
124 return -1;
125 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000126 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000127}
128
Ollie Lho184a4042005-11-26 21:55:36 +0000129int write_29f040b(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000130{
131 int i;
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000132 int total_size = flash->total_size * 1024;
133 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000134 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000135
Stefan Reinauer99349a52006-03-16 16:46:19 +0000136 printf("Programming page ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000137 for (i = 0; i < total_size / page_size; i++) {
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000138 /* erase the page before programming */
Sean Nelson72a9a022009-12-22 22:15:33 +0000139 if (erase_sector_29f040b(flash, i * page_size, page_size)) {
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000140 fprintf(stderr, "ERASE FAILED!\n");
141 return -1;
142 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000143
144 /* write to the sector */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000145 printf("%04d at address: ", i);
146 write_sector_29f040b(bios, buf + i * page_size,
147 bios + i * page_size, page_size);
148 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000149 }
150 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000151
Uwe Hermannffec5f32007-08-23 16:08:21 +0000152 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000153}