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review.sourcearcade.org / libgfxinit / be4eaddc67ee3a11b1222db049cd8830491363d9 / . / common / hw-gfx-gma-registers.ads
blob: a765e2d73607bc4019b9e31d0da3d85b6136a847 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
6-- the Free Software Foundation; version 2 of the License.
7--
8-- This program is distributed in the hope that it will be useful,
9-- but WITHOUT ANY WARRANTY; without even the implied warranty of
10-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11-- GNU General Public License for more details.
12--
13
14with System;
15with HW.GFX.GMA;
16with HW.GFX.GMA.Config;
17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
47 MBCTL,
48 UCGCTL1,
49 UCGCTL2,
50 VCS_RING_BUFFER_TAIL,
51 VCS_RING_BUFFER_HEAD,
52 VCS_RING_BUFFER_STRT,
53 VCS_RING_BUFFER_CTL,
54 SLEEP_PSMI_CONTROL,
55 VCS_HWSTAM,
56 VCS_PP_DCLV_HIGH,
57 VCS_PP_DCLV_LOW,
58 GAC_ECO_BITS,
59 BCS_RING_BUFFER_TAIL,
60 BCS_RING_BUFFER_HEAD,
61 BCS_RING_BUFFER_STRT,
62 BCS_RING_BUFFER_CTL,
63 BCS_HWSTAM,
64 BCS_PP_DCLV_HIGH,
65 BCS_PP_DCLV_LOW,
66 GAB_CTL_REG,
67 VGACNTRL,
68 FUSE_STATUS,
69 QUIRK_42004,
70 DSPCLK_GATE_D,
71 FBA_CFB_BASE,
72 FBC_CTL,
73 IPS_CTL,
74 DEISR,
75 DEIMR,
76 DEIIR,
77 DEIER,
78 GTISR,
79 GTIMR,
80 GTIIR,
81 GTIER,
82 IIR,
83 HOTPLUG_CTL,
84 ARB_CTL,
85 DBUF_CTL,
86 WM_PIPE_A,
87 WM_PIPE_B,
88 WM1_LP_ILK,
89 WM2_LP_ILK,
90 WM3_LP_ILK,
91 WM_PIPE_C,
92 WM_LINETIME_A,
93 WM_LINETIME_B,
94 WM_LINETIME_C,
95 PWR_WELL_CTL_BIOS,
96 PWR_WELL_CTL_DRIVER,
97 PWR_WELL_CTL_KVMR,
98 PWR_WELL_CTL_DEBUG,
99 PWR_WELL_CTL5,
100 PWR_WELL_CTL6,
101 CDCLK_CTL,
102 LCPLL1_CTL,
103 LCPLL2_CTL,
104 SPLL_CTL,
105 WRPLL_CTL_1,
106 WRPLL_CTL_2,
107 PORT_CLK_SEL_DDIA,
108 PORT_CLK_SEL_DDIB,
109 PORT_CLK_SEL_DDIC,
110 PORT_CLK_SEL_DDID,
111 PORT_CLK_SEL_DDIE,
112 TRANSA_CLK_SEL,
113 TRANSB_CLK_SEL,
114 TRANSC_CLK_SEL,
115 NDE_RSTWRN_OPT,
116 BLC_PWM_CPU_CTL2,
117 BLC_PWM_CPU_CTL,
118 HTOTAL_A,
119 HBLANK_A,
120 HSYNC_A,
121 VTOTAL_A,
122 VBLANK_A,
123 VSYNC_A,
124 PIPEASRC,
125 PIPE_VSYNCSHIFT_A,
126 PIPEA_DATA_M1,
127 PIPEA_DATA_N1,
128 PIPEA_LINK_M1,
129 PIPEA_LINK_N1,
130 FDI_TX_CTL_A,
131 PIPEA_DDI_FUNC_CTL,
132 PIPEA_MSA_MISC,
133 SRD_CTL_A,
134 SRD_STATUS_A,
135 HTOTAL_B,
136 HBLANK_B,
137 HSYNC_B,
138 VTOTAL_B,
139 VBLANK_B,
140 VSYNC_B,
141 PIPEBSRC,
142 PIPE_VSYNCSHIFT_B,
143 PIPEB_DATA_M1,
144 PIPEB_DATA_N1,
145 PIPEB_LINK_M1,
146 PIPEB_LINK_N1,
147 FDI_TX_CTL_B,
148 PIPEB_DDI_FUNC_CTL,
149 PIPEB_MSA_MISC,
150 SRD_CTL_B,
151 SRD_STATUS_B,
152 HTOTAL_C,
153 HBLANK_C,
154 HSYNC_C,
155 VTOTAL_C,
156 VBLANK_C,
157 VSYNC_C,
158 PIPECSRC,
159 PIPE_VSYNCSHIFT_C,
160 PIPEC_DATA_M1,
161 PIPEC_DATA_N1,
162 PIPEC_LINK_M1,
163 PIPEC_LINK_N1,
164 FDI_TX_CTL_C,
165 PIPEC_DDI_FUNC_CTL,
166 PIPEC_MSA_MISC,
167 SRD_CTL_C,
168 SRD_STATUS_C,
169 DDI_BUF_CTL_A,
170 DDI_AUX_CTL_A,
171 DDI_AUX_DATA_A_1,
172 DDI_AUX_DATA_A_2,
173 DDI_AUX_DATA_A_3,
174 DDI_AUX_DATA_A_4,
175 DDI_AUX_DATA_A_5,
176 DDI_AUX_MUTEX_A,
177 DP_TP_CTL_A,
178 DDI_BUF_CTL_B,
179 DDI_AUX_CTL_B,
180 DDI_AUX_DATA_B_1,
181 DDI_AUX_DATA_B_2,
182 DDI_AUX_DATA_B_3,
183 DDI_AUX_DATA_B_4,
184 DDI_AUX_DATA_B_5,
185 DDI_AUX_MUTEX_B,
186 DP_TP_CTL_B,
187 DP_TP_STATUS_B,
188 DDI_BUF_CTL_C,
189 DDI_AUX_CTL_C,
190 DDI_AUX_DATA_C_1,
191 DDI_AUX_DATA_C_2,
192 DDI_AUX_DATA_C_3,
193 DDI_AUX_DATA_C_4,
194 DDI_AUX_DATA_C_5,
195 DDI_AUX_MUTEX_C,
196 DP_TP_CTL_C,
197 DP_TP_STATUS_C,
198 DDI_BUF_CTL_D,
199 DDI_AUX_CTL_D,
200 DDI_AUX_DATA_D_1,
201 DDI_AUX_DATA_D_2,
202 DDI_AUX_DATA_D_3,
203 DDI_AUX_DATA_D_4,
204 DDI_AUX_DATA_D_5,
205 DDI_AUX_MUTEX_D,
206 DP_TP_CTL_D,
207 DP_TP_STATUS_D,
208 DDI_BUF_CTL_E,
209 DP_TP_CTL_E,
210 DP_TP_STATUS_E,
211 SRD_CTL,
212 SRD_STATUS,
213 AUD_VID_DID,
214 PFA_WIN_POS,
215 PFA_WIN_SZ,
216 PFA_CTL_1,
217 PS_WIN_POS_1_A,
218 PS_WIN_SZ_1_A,
219 PS_CTRL_1_A,
220 PS_WIN_POS_2_A,
221 PS_WIN_SZ_2_A,
222 PS_CTRL_2_A,
223 PFB_WIN_POS,
224 PFB_WIN_SZ,
225 PFB_CTL_1,
226 PS_WIN_POS_1_B,
227 PS_WIN_SZ_1_B,
228 PS_CTRL_1_B,
229 PS_WIN_POS_2_B,
230 PS_WIN_SZ_2_B,
231 PS_CTRL_2_B,
232 PFC_WIN_POS,
233 PFC_WIN_SZ,
234 PFC_CTL_1,
235 PS_WIN_POS_1_C,
236 PS_WIN_SZ_1_C,
237 PS_CTRL_1_C,
238 DPLL1_CFGR1,
239 DPLL1_CFGR2,
240 DPLL2_CFGR1,
241 DPLL2_CFGR2,
242 DPLL3_CFGR1,
243 DPLL3_CFGR2,
244 DPLL_CTRL1,
245 DPLL_CTRL2,
246 DPLL_STATUS,
247 HTOTAL_EDP,
248 HBLANK_EDP,
249 HSYNC_EDP,
250 VTOTAL_EDP,
251 VBLANK_EDP,
252 VSYNC_EDP,
253 PIPE_EDP_DATA_M1,
254 PIPE_EDP_DATA_N1,
255 PIPE_EDP_LINK_M1,
256 PIPE_EDP_LINK_N1,
257 PIPE_EDP_DDI_FUNC_CTL,
258 PIPE_EDP_MSA_MISC,
259 SRD_CTL_EDP,
260 SRD_STATUS_EDP,
261 PIPE_SCANLINE_A,
262 PIPEACONF,
263 PIPEAMISC,
264 PIPE_FRMCNT_A,
265 DSPACNTR,
266 DSPALINOFF,
267 DSPASTRIDE,
268 PLANE_POS_1_A,
269 PLANE_SIZE_1_A,
270 DSPASURF,
271 DSPATILEOFF,
272 PLANE_WM_1_A_0,
273 PLANE_WM_1_A_1,
274 PLANE_WM_1_A_2,
275 PLANE_WM_1_A_3,
276 PLANE_WM_1_A_4,
277 PLANE_WM_1_A_5,
278 PLANE_WM_1_A_6,
279 PLANE_WM_1_A_7,
280 PLANE_BUF_CFG_1_A,
281 SPACNTR,
282 PIPE_SCANLINE_B,
283 PIPEBCONF,
284 PIPEBMISC,
285 PIPE_FRMCNT_B,
286 DSPBCNTR,
287 DSPBLINOFF,
288 DSPBSTRIDE,
289 PLANE_POS_1_B,
290 PLANE_SIZE_1_B,
291 DSPBSURF,
292 DSPBTILEOFF,
293 PLANE_WM_1_B_0,
294 PLANE_WM_1_B_1,
295 PLANE_WM_1_B_2,
296 PLANE_WM_1_B_3,
297 PLANE_WM_1_B_4,
298 PLANE_WM_1_B_5,
299 PLANE_WM_1_B_6,
300 PLANE_WM_1_B_7,
301 PLANE_BUF_CFG_1_B,
302 SPBCNTR,
303 PIPE_SCANLINE_C,
304 PIPECCONF,
305 PIPECMISC,
306 PIPE_FRMCNT_C,
307 DSPCCNTR,
308 DSPCLINOFF,
309 DSPCSTRIDE,
310 PLANE_POS_1_C,
311 PLANE_SIZE_1_C,
312 DSPCSURF,
313 DSPCTILEOFF,
314 PLANE_WM_1_C_0,
315 PLANE_WM_1_C_1,
316 PLANE_WM_1_C_2,
317 PLANE_WM_1_C_3,
318 PLANE_WM_1_C_4,
319 PLANE_WM_1_C_5,
320 PLANE_WM_1_C_6,
321 PLANE_WM_1_C_7,
322 PLANE_BUF_CFG_1_C,
323 SPCCNTR,
324 PIPE_EDP_CONF,
325 PCH_FDI_CHICKEN_B_C,
326 QUIRK_C2004,
327 SFUSE_STRAP,
328 PCH_DSPCLK_GATE_D,
329 SDEISR,
330 SDEIMR,
331 SDEIIR,
332 SDEIER,
333 SHOTPLUG_CTL,
334 PCH_GMBUS0,
335 PCH_GMBUS1,
336 PCH_GMBUS2,
337 PCH_GMBUS3,
338 PCH_GMBUS4,
339 PCH_GMBUS5,
340 SBI_ADDR,
341 SBI_DATA,
342 SBI_CTL_STAT,
343 PCH_DPLL_A,
344 PCH_DPLL_B,
345 PCH_PIXCLK_GATE,
346 PCH_FPA0,
347 PCH_FPA1,
348 PCH_FPB0,
349 PCH_FPB1,
350 PCH_DREF_CONTROL,
351 RAWCLK_FREQ,
352 PCH_DPLL_SEL,
353 PCH_PP_STATUS,
354 PCH_PP_CONTROL,
355 PCH_PP_ON_DELAYS,
356 PCH_PP_OFF_DELAYS,
357 PCH_PP_DIVISOR,
358 BLC_PWM_PCH_CTL1,
359 BLC_PWM_PCH_CTL2,
360 TRANS_HTOTAL_A,
361 TRANS_HBLANK_A,
362 TRANS_HSYNC_A,
363 TRANS_VTOTAL_A,
364 TRANS_VBLANK_A,
365 TRANS_VSYNC_A,
366 TRANS_VSYNCSHIFT_A,
367 TRANSA_DATA_M1,
368 TRANSA_DATA_N1,
369 TRANSA_DP_LINK_M1,
370 TRANSA_DP_LINK_N1,
371 TRANS_DP_CTL_A,
372 TRANS_HTOTAL_B,
373 TRANS_HBLANK_B,
374 TRANS_HSYNC_B,
375 TRANS_VTOTAL_B,
376 TRANS_VBLANK_B,
377 TRANS_VSYNC_B,
378 TRANS_VSYNCSHIFT_B,
379 TRANSB_DATA_M1,
380 TRANSB_DATA_N1,
381 TRANSB_DP_LINK_M1,
382 TRANSB_DP_LINK_N1,
383 PCH_ADPA,
384 PCH_HDMIB,
385 PCH_HDMIC,
386 PCH_HDMID,
387 PCH_LVDS,
388 TRANS_DP_CTL_B,
389 TRANS_HTOTAL_C,
390 TRANS_HBLANK_C,
391 TRANS_HSYNC_C,
392 TRANS_VTOTAL_C,
393 TRANS_VBLANK_C,
394 TRANS_VSYNC_C,
395 TRANS_VSYNCSHIFT_C,
396 TRANSC_DATA_M1,
397 TRANSC_DATA_N1,
398 TRANSC_DP_LINK_M1,
399 TRANSC_DP_LINK_N1,
400 TRANS_DP_CTL_C,
401 PCH_DP_B,
402 PCH_DP_AUX_CTL_B,
403 PCH_DP_AUX_DATA_B_1,
404 PCH_DP_AUX_DATA_B_2,
405 PCH_DP_AUX_DATA_B_3,
406 PCH_DP_AUX_DATA_B_4,
407 PCH_DP_AUX_DATA_B_5,
408 PCH_DP_C,
409 PCH_DP_AUX_CTL_C,
410 PCH_DP_AUX_DATA_C_1,
411 PCH_DP_AUX_DATA_C_2,
412 PCH_DP_AUX_DATA_C_3,
413 PCH_DP_AUX_DATA_C_4,
414 PCH_DP_AUX_DATA_C_5,
415 PCH_DP_D,
416 PCH_DP_AUX_CTL_D,
417 PCH_DP_AUX_DATA_D_1,
418 PCH_DP_AUX_DATA_D_2,
419 PCH_DP_AUX_DATA_D_3,
420 PCH_DP_AUX_DATA_D_4,
421 PCH_DP_AUX_DATA_D_5,
422 AUD_CONFIG_A,
423 PCH_AUD_VID_DID,
424 AUD_HDMIW_HDMIEDID_A,
425 AUD_CNTL_ST_A,
426 AUD_CNTRL_ST2,
427 AUD_CONFIG_B,
428 AUD_HDMIW_HDMIEDID_B,
429 AUD_CNTL_ST_B,
430 AUD_CONFIG_C,
431 AUD_HDMIW_HDMIEDID_C,
432 AUD_CNTL_ST_C,
433 TRANSACONF,
434 FDI_RXA_CTL,
435 FDI_RX_MISC_A,
436 FDI_RXA_IIR,
437 FDI_RXA_IMR,
438 FDI_RXA_TUSIZE1,
439 QUIRK_F0060,
440 TRANSA_CHICKEN2,
441 TRANSBCONF,
442 FDI_RXB_CTL,
443 FDI_RX_MISC_B,
444 FDI_RXB_IIR,
445 FDI_RXB_IMR,
446 FDI_RXB_TUSIZE1,
447 QUIRK_F1060,
448 TRANSB_CHICKEN2,
449 TRANSCCONF,
450 FDI_RXC_CTL,
451 FDI_RX_MISC_C,
452 FDI_RXC_IIR,
453 FDI_RXC_IMR,
454 FDI_RXC_TUSIZE1,
455 QUIRK_F2060,
456 TRANSC_CHICKEN2,
457 GT_MAILBOX,
458 GT_MAILBOX_DATA,
459 GT_MAILBOX_DATA_1);
460
461 pragma Warnings
462 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
463 Reason => "TODO: Should it matter?");
464 pragma Keep_Names (Registers_Invalid_Index);
465 pragma Warnings
466 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
467
468 Register_Width : constant := 4;
469
470 for Registers_Invalid_Index use
471 (Invalid_Register => 0,
472
473 ---------------------------------------------------------------------------
474 -- Pipe A registers
475 ---------------------------------------------------------------------------
476
477 -- pipe timing registers
478
479 HTOTAL_A => 16#06_0000# / Register_Width,
480 HBLANK_A => 16#06_0004# / Register_Width,
481 HSYNC_A => 16#06_0008# / Register_Width,
482 VTOTAL_A => 16#06_000c# / Register_Width,
483 VBLANK_A => 16#06_0010# / Register_Width,
484 VSYNC_A => 16#06_0014# / Register_Width,
485 PIPEASRC => 16#06_001c# / Register_Width,
486 PIPEACONF => 16#07_0008# / Register_Width,
487 PIPEAMISC => 16#07_0030# / Register_Width,
488 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
489 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
490 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
491 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
492 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
493 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
494 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
495 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
496 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
497 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
498 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
499 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
500 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
501 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
502 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
503 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
504
505 -- PCH sideband interface registers
506 SBI_ADDR => 16#0c_6000# / Register_Width,
507 SBI_DATA => 16#0c_6004# / Register_Width,
508 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
509
510 -- clock registers
511 PCH_DPLL_A => 16#0c_6014# / Register_Width,
512 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
513 PCH_FPA0 => 16#0c_6040# / Register_Width,
514 PCH_FPA1 => 16#0c_6044# / Register_Width,
515
516 -- panel fitter
517 PFA_CTL_1 => 16#06_8080# / Register_Width,
518 PFA_WIN_POS => 16#06_8070# / Register_Width,
519 PFA_WIN_SZ => 16#06_8074# / Register_Width,
520 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
521 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
522 PS_CTRL_1_A => 16#06_8180# / Register_Width,
523 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
524 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
525 PS_CTRL_2_A => 16#06_8280# / Register_Width,
526
527 -- display control
528 DSPACNTR => 16#07_0180# / Register_Width,
529 DSPALINOFF => 16#07_0184# / Register_Width,
530 DSPASTRIDE => 16#07_0188# / Register_Width,
531 PLANE_POS_1_A => 16#07_018c# / Register_Width,
532 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
533 DSPASURF => 16#07_019c# / Register_Width,
534 DSPATILEOFF => 16#07_01a4# / Register_Width,
535
536 -- sprite control
537 SPACNTR => 16#07_0280# / Register_Width,
538
539 -- FDI and PCH transcoder control
540 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
541 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
542 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
543 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
544 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
545 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
546 TRANSACONF => 16#0f_0008# / Register_Width,
547 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
548
549 -- watermark registers
550 WM_LINETIME_A => 16#04_5270# / Register_Width,
551 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
552 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
553 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
554 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
555 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
556 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
557 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
558 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
559 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
560
561 -- CPU transcoder clock select
562 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
563
564 ---------------------------------------------------------------------------
565 -- Pipe B registers
566 ---------------------------------------------------------------------------
567
568 -- pipe timing registers
569
570 HTOTAL_B => 16#06_1000# / Register_Width,
571 HBLANK_B => 16#06_1004# / Register_Width,
572 HSYNC_B => 16#06_1008# / Register_Width,
573 VTOTAL_B => 16#06_100c# / Register_Width,
574 VBLANK_B => 16#06_1010# / Register_Width,
575 VSYNC_B => 16#06_1014# / Register_Width,
576 PIPEBSRC => 16#06_101c# / Register_Width,
577 PIPEBCONF => 16#07_1008# / Register_Width,
578 PIPEBMISC => 16#07_1030# / Register_Width,
579 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
580 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
581 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
582 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
583 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
584 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
585 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
586 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
587 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
588 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
589 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
590 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
591 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
592 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
593 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
594 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
595
596 -- clock registers
597 PCH_DPLL_B => 16#0c_6018# / Register_Width,
598 PCH_FPB0 => 16#0c_6048# / Register_Width,
599 PCH_FPB1 => 16#0c_604c# / Register_Width,
600
601 -- panel fitter
602 PFB_CTL_1 => 16#06_8880# / Register_Width,
603 PFB_WIN_POS => 16#06_8870# / Register_Width,
604 PFB_WIN_SZ => 16#06_8874# / Register_Width,
605 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
606 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
607 PS_CTRL_1_B => 16#06_8980# / Register_Width,
608 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
609 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
610 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
611
612 -- display control
613 DSPBCNTR => 16#07_1180# / Register_Width,
614 DSPBLINOFF => 16#07_1184# / Register_Width,
615 DSPBSTRIDE => 16#07_1188# / Register_Width,
616 PLANE_POS_1_B => 16#07_118c# / Register_Width,
617 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
618 DSPBSURF => 16#07_119c# / Register_Width,
619 DSPBTILEOFF => 16#07_11a4# / Register_Width,
620
621 -- sprite control
622 SPBCNTR => 16#07_1280# / Register_Width,
623
624 -- FDI and PCH transcoder control
625 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
626 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
627 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
628 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
629 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
630 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
631 TRANSBCONF => 16#0f_1008# / Register_Width,
632 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
633
634 -- watermark registers
635 WM_LINETIME_B => 16#04_5274# / Register_Width,
636 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
637 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
638 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
639 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
640 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
641 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
642 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
643 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
644 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
645
646 -- CPU transcoder clock select
647 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
648
649 ---------------------------------------------------------------------------
650 -- Pipe C registers
651 ---------------------------------------------------------------------------
652
653 -- pipe timing registers
654
655 HTOTAL_C => 16#06_2000# / Register_Width,
656 HBLANK_C => 16#06_2004# / Register_Width,
657 HSYNC_C => 16#06_2008# / Register_Width,
658 VTOTAL_C => 16#06_200c# / Register_Width,
659 VBLANK_C => 16#06_2010# / Register_Width,
660 VSYNC_C => 16#06_2014# / Register_Width,
661 PIPECSRC => 16#06_201c# / Register_Width,
662 PIPECCONF => 16#07_2008# / Register_Width,
663 PIPECMISC => 16#07_2030# / Register_Width,
664 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
665 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
666 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
667 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
668 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
669 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
670 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
671 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
672 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
673 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
674 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
675 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
676 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
677 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
678 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
679 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
680
681 -- panel fitter
682 PFC_CTL_1 => 16#06_9080# / Register_Width,
683 PFC_WIN_POS => 16#06_9070# / Register_Width,
684 PFC_WIN_SZ => 16#06_9074# / Register_Width,
685 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
686 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
687 PS_CTRL_1_C => 16#06_9180# / Register_Width,
688
689 -- display control
690 DSPCCNTR => 16#07_2180# / Register_Width,
691 DSPCLINOFF => 16#07_2184# / Register_Width,
692 DSPCSTRIDE => 16#07_2188# / Register_Width,
693 PLANE_POS_1_C => 16#07_218c# / Register_Width,
694 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
695 DSPCSURF => 16#07_219c# / Register_Width,
696 DSPCTILEOFF => 16#07_21a4# / Register_Width,
697
698 -- sprite control
699 SPCCNTR => 16#07_2280# / Register_Width,
700
701 -- PCH transcoder control
702 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
703 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
704 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
705 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
706 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
707 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
708 TRANSCCONF => 16#0f_2008# / Register_Width,
709 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
710
711 -- watermark registers
712 WM_LINETIME_C => 16#04_5278# / Register_Width,
713 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
714 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
715 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
716 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
717 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
718 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
719 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
720 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
721 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
722
723 -- CPU transcoder clock select
724 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
725
726 ---------------------------------------------------------------------------
727 -- Pipe EDP registers
728 ---------------------------------------------------------------------------
729
730 -- pipe timing registers
731
732 HTOTAL_EDP => 16#06_f000# / Register_Width,
733 HBLANK_EDP => 16#06_f004# / Register_Width,
734 HSYNC_EDP => 16#06_f008# / Register_Width,
735 VTOTAL_EDP => 16#06_f00c# / Register_Width,
736 VBLANK_EDP => 16#06_f010# / Register_Width,
737 VSYNC_EDP => 16#06_f014# / Register_Width,
738 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
739 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
740 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
741 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
742 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
743 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
744 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
745
746 -- PSR registers
747 SRD_CTL => 16#06_4800# / Register_Width,
748 SRD_CTL_A => 16#06_0800# / Register_Width,
749 SRD_CTL_B => 16#06_1800# / Register_Width,
750 SRD_CTL_C => 16#06_2800# / Register_Width,
751 SRD_CTL_EDP => 16#06_f800# / Register_Width,
752 SRD_STATUS => 16#06_4840# / Register_Width,
753 SRD_STATUS_A => 16#06_0840# / Register_Width,
754 SRD_STATUS_B => 16#06_1840# / Register_Width,
755 SRD_STATUS_C => 16#06_2840# / Register_Width,
756 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
757
758 -- DDI registers
759 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
760 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
761 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
762 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
763 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
764 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
765 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
766 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
767 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
768 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
769 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
770 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
771 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
772 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
773 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
774 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
775 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
776 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
777 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
778 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
779 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
780 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
781 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
782 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
783 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
784 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
785 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
786 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
787 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
788 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
789 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
790 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
791 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
792 DP_TP_CTL_A => 16#06_4040# / Register_Width,
793 DP_TP_CTL_B => 16#06_4140# / Register_Width,
794 DP_TP_CTL_C => 16#06_4240# / Register_Width,
795 DP_TP_CTL_D => 16#06_4340# / Register_Width,
796 DP_TP_CTL_E => 16#06_4440# / Register_Width,
797 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
798 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
799 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
800 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
801 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
802 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
803 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
804 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
805 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
806
807 -- Skylake DPLL registers
808 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
809 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
810 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
811 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
812 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
813 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
814 DPLL_CTRL1 => 16#06_c058# / Register_Width,
815 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
816 DPLL_STATUS => 16#06_c060# / Register_Width,
817
818 -- CD CLK register
819 CDCLK_CTL => 16#04_6000# / Register_Width,
820
821 -- Skylake LCPLL registers
822 LCPLL1_CTL => 16#04_6010# / Register_Width,
823 LCPLL2_CTL => 16#04_6014# / Register_Width,
824
825 -- SPLL register
826 SPLL_CTL => 16#04_6020# / Register_Width,
827
828 -- WRPLL registers
829 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
830 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
831
832 -- Power Down Well registers
833 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
834 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
835 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
836 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
837 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
838 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
839
840 -- class Panel registers
841 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
842 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
843 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
844 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
845 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
846 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
847 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
848
849 -- PCH LVDS Connector Registers
850 PCH_LVDS => 16#0e_1180# / Register_Width,
851
852 -- PCH ADPA Connector Registers
853 PCH_ADPA => 16#0e_1100# / Register_Width,
854
855 -- PCH HDMIB Connector Registers
856 PCH_HDMIB => 16#0e_1140# / Register_Width,
857
858 -- PCH HDMIC Connector Registers
859 PCH_HDMIC => 16#0e_1150# / Register_Width,
860
861 -- PCH HDMID Connector Registers
862 PCH_HDMID => 16#0e_1160# / Register_Width,
863
864 -- Intel Registers
865 VGACNTRL => 16#04_1000# / Register_Width,
866 FUSE_STATUS => 16#04_2000# / Register_Width,
867 FBA_CFB_BASE => 16#04_3200# / Register_Width,
868 IPS_CTL => 16#04_3408# / Register_Width,
869 ARB_CTL => 16#04_5000# / Register_Width,
870 DBUF_CTL => 16#04_5008# / Register_Width,
871 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
872 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
873 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
874 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
875 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
876 GT_MAILBOX => 16#13_8124# / Register_Width,
877 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
878 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
879
880 PCH_DP_B => 16#0e_4100# / Register_Width,
881 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
882 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
883 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
884 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
885 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
886 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
887 PCH_DP_C => 16#0e_4200# / Register_Width,
888 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
889 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
890 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
891 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
892 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
893 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
894 PCH_DP_D => 16#0e_4300# / Register_Width,
895 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
896 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
897 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
898 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
899 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
900 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
901
902 -- watermark registers
903 WM1_LP_ILK => 16#04_5108# / Register_Width,
904 WM2_LP_ILK => 16#04_510c# / Register_Width,
905 WM3_LP_ILK => 16#04_5110# / Register_Width,
906
907 -- audio VID/DID
908 AUD_VID_DID => 16#06_5020# / Register_Width,
909 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
910
911 -- interrupt registers
912 DEISR => 16#04_4000# / Register_Width,
913 DEIMR => 16#04_4004# / Register_Width,
914 DEIIR => 16#04_4008# / Register_Width,
915 DEIER => 16#04_400c# / Register_Width,
916 GTISR => 16#04_4010# / Register_Width,
917 GTIMR => 16#04_4014# / Register_Width,
918 GTIIR => 16#04_4018# / Register_Width,
919 GTIER => 16#04_401c# / Register_Width,
920 SDEISR => 16#0c_4000# / Register_Width,
921 SDEIMR => 16#0c_4004# / Register_Width,
922 SDEIIR => 16#0c_4008# / Register_Width,
923 SDEIER => 16#0c_400c# / Register_Width,
924
925 -- I2C stuff
926 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
927 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
928 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
929 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
930 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
931 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
932
933 -- clock gating -- maybe have to touch this
934 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
935 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
936 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
937
938 -- hotplug and initial detection
939 HOTPLUG_CTL => 16#04_4030# / Register_Width,
940 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
941 SFUSE_STRAP => 16#0c_2014# / Register_Width,
942
943 -- Render Engine Command Streamer
944 ARB_MODE => 16#00_4030# / Register_Width,
945 HWS_PGA => 16#00_4080# / Register_Width,
946 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
947 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
948 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
949 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
950 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
951 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
952 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
953 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
954 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
955 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
956 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
957 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
958 MI_MODE => 16#00_209c# / Register_Width,
959 INSTPM => 16#00_20c0# / Register_Width,
960 GAB_CTL_REG => 16#02_4000# / Register_Width,
961 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
962 PP_DCLV_LOW => 16#00_2228# / Register_Width,
963 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
964 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
965 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
966 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
967 QUIRK_42004 => 16#04_2004# / Register_Width,
968 UCGCTL1 => 16#00_9400# / Register_Width,
969 UCGCTL2 => 16#00_9404# / Register_Width,
970 MBCTL => 16#00_907c# / Register_Width,
971 HWSTAM => 16#00_2098# / Register_Width,
972 VCS_HWSTAM => 16#01_2098# / Register_Width,
973 BCS_HWSTAM => 16#02_2098# / Register_Width,
974 IIR => 16#04_4028# / Register_Width,
975 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
976 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
977 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
978 FBC_CTL => 16#04_3208# / Register_Width,
979 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
980 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
981 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
982 WM_PIPE_A => 16#04_5100# / Register_Width,
983 WM_PIPE_B => 16#04_5104# / Register_Width,
984 WM_PIPE_C => 16#04_5200# / Register_Width,
985 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
986 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
987 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
988 GFX_MODE => 16#00_2520# / Register_Width,
989 CACHE_MODE_0 => 16#00_2120# / Register_Width,
990 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
991 CTX_SIZE => 16#00_21a0# / Register_Width,
992 GAC_ECO_BITS => 16#01_4090# / Register_Width,
993 GAM_ECOCHK => 16#00_4090# / Register_Width,
994 QUIRK_02084 => 16#00_2084# / Register_Width,
995 QUIRK_02090 => 16#00_2090# / Register_Width,
996 GT_MODE => 16#00_20d0# / Register_Width,
997 QUIRK_F0060 => 16#0f_0060# / Register_Width,
998 QUIRK_F1060 => 16#0f_1060# / Register_Width,
999 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1000 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1001 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1002 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1003 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1004 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1005 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1006 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1007 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1008 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1009 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1010 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1011 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1012 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1013 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1014 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1015 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
1016 RAWCLK_FREQ => 16#0c_6204# / Register_Width,
1017 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1018
1019 subtype Registers_Index is Registers_Invalid_Index range
1020 Registers_Invalid_Index'Succ (Invalid_Register) ..
1021 Registers_Invalid_Index'Last;
1022
1023 -- aliased registers
1024 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1025 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1026 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1027 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1028 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1029 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1030 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
1031
1032 ---------------------------------------------------------------------------
1033
1034 Default_Timeout_MS : constant := 10;
1035
1036 ---------------------------------------------------------------------------
1037
1038 procedure Posting_Read
1039 (Register : in Registers_Index)
1040 with
1041 Global => (In_Out => Register_State),
1042 Depends => (Register_State =>+ (Register)),
1043 Pre => True,
1044 Post => True;
1045
1046 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1047 Reason => "Only used on debugging path");
1048 procedure Read
1049 (Register : in Registers_Index;
1050 Value : out Word32;
1051 Verbose : in Boolean := True)
1052 with
1053 Global => (In_Out => Register_State),
1054 Depends => ((Value, Register_State) => (Register, Register_State),
1055 null => Verbose),
1056 Pre => True,
1057 Post => True;
1058 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1059
1060 procedure Write
1061 (Register : Registers_Index;
1062 Value : Word32)
1063 with
1064 Global => (In_Out => Register_State),
1065 Depends => (Register_State => (Register, Register_State, Value)),
1066 Pre => True,
1067 Post => True;
1068
1069 procedure Is_Set_Mask
1070 (Register : in Registers_Index;
1071 Mask : in Word32;
1072 Result : out Boolean);
1073
1074 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1075 Reason => "Only used on debugging path");
1076 procedure Wait_Set_Mask
1077 (Register : Registers_Index;
1078 Mask : Word32;
1079 TOut_MS : Natural := Default_Timeout_MS;
1080 Verbose : Boolean := False);
1081
1082 procedure Wait_Unset_Mask
1083 (Register : Registers_Index;
1084 Mask : Word32;
1085 TOut_MS : Natural := Default_Timeout_MS;
1086 Verbose : Boolean := False);
1087 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1088
1089 procedure Set_Mask
1090 (Register : Registers_Index;
1091 Mask : Word32);
1092
1093 procedure Unset_Mask
1094 (Register : Registers_Index;
1095 Mask : Word32);
1096
1097 procedure Unset_And_Set_Mask
1098 (Register : Registers_Index;
1099 Mask_Unset : Word32;
1100 Mask_Set : Word32);
1101
1102 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1103 procedure Write_GTT
1104 (GTT_Page : GTT_Range;
1105 Device_Address : GTT_Address_Type;
1106 Valid : Boolean)
1107 with
1108 Global => (In_Out => GTT_State),
1109 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1110 Pre => True,
1111 Post => True;
1112 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1113
1114 procedure Set_Register_Base (Base : Word64)
1115 with
1116 Global => (Output => Address_State),
1117 Depends => (Address_State => Base),
1118 Pre => True,
1119 Post => True;
1120
1121end HW.GFX.GMA.Registers;