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review.sourcearcade.org / libgfxinit / be4eaddc67ee3a11b1222db049cd8830491363d9 / . / common / hw-gfx-gma-config.ads.template
blob: 00418cd9afea9b833496ab34dde9b9bafdc4c8db [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
6-- the Free Software Foundation; version 2 of the License.
7--
8-- This program is distributed in the hope that it will be useful,
9-- but WITHOUT ANY WARRANTY; without even the implied warranty of
10-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11-- GNU General Public License for more details.
12--
13
14private package HW.GFX.GMA.Config
15with
16 Initializes => Valid_Port_GPU
17is
18
19 CPU : constant CPU_Type := <<CPU>>;
20
21 CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>;
22
23 Internal_Display : constant Internal_Type := <<INTERNAL_PORT>>;
24
25 EDP_Low_Voltage_Swing : constant Boolean := False;
26
27 Default_MMIO_Base : constant := <<DEFAULT_MMIO_BASE>>;
28
29 LVDS_Dual_Threshold : constant := 95_000_000;
30
31 ----------------------------------------------------------------------------
32
33 Has_Internal_Display : constant Boolean := Internal_Display /= None;
34 Internal_Is_EDP : constant Boolean := Internal_Display = DP;
35
36 ----- CPU pipe: --------
37 Disable_Trickle_Feed : constant Boolean := not
38 (CPU in Haswell .. Broadwell);
39 Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell;
40 Has_EDP_Pipe : constant Boolean := CPU >= Haswell;
41 Has_Pipe_DDI_Func : constant Boolean := CPU >= Haswell;
42 Has_Trans_Clk_Sel : constant Boolean := CPU >= Haswell;
43 Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell;
44 Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell;
45 Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell;
46 Has_Plane_Control : constant Boolean := CPU >= Skylake;
47 Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge;
48
49 ----- Panel power: -----
50 Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge;
51 Has_PP_Port_Select : constant Boolean := CPU <= Ivybridge;
52 Use_PP_VDD_Override : constant Boolean := CPU <= Ivybridge;
53
54 ----- PCH/FDI: ---------
55 Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or
56 (CPU in Broadwell .. Haswell
57 and CPU_Var = Normal);
58
59 Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell;
60
61 VGA_Has_Sync_Disable : constant Boolean := CPU <= Ivybridge;
62
63 Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge;
64
65 Has_DPLL_SEL : constant Boolean := CPU in Ironlake .. Ivybridge;
66 Has_FDI_BPC : constant Boolean := CPU in Ironlake .. Ivybridge;
67 Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge;
68 Has_Trans_DP_Ctl : constant Boolean := CPU in
69 Sandybridge .. Ivybridge;
70 Has_FDI_C : constant Boolean := CPU = Ivybridge;
71
72 Has_FDI_RX_Power_Down : constant Boolean := CPU in Haswell .. Broadwell;
73
74 ----- DDI: -------------
75 End_EDP_Training_Late : constant Boolean := CPU in Haswell .. Broadwell;
76 Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell;
77 Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell;
78 Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell
79 and CPU_Var = ULT) or
80 CPU >= Skylake;
81
82 Has_DDI_D : constant Boolean := (CPU in Haswell .. Broadwell
83 and CPU_Var = Normal)
84 or CPU >= Skylake;
85
86 Has_Low_Voltage_Swing : constant Boolean := CPU >= Skylake;
87
88 Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC)
89
90 Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake;
91
92 ----- Power: -----------
93 Has_IPS : constant Boolean := (CPU = Haswell and
94 CPU_Var = ULT) or
95 CPU = Broadwell;
96 Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell;
97
98 Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell;
99
100 ----- GTT: -----
101 Fold_39Bit_GTT_PTE : constant Boolean := CPU <= Haswell;
102
103 ----------------------------------------------------------------------------
104
105 type Supported_Pipe_Array is array (Config_Index) of Boolean;
106 Supported_Pipe : constant Supported_Pipe_Array :=
107 (Primary => True,
108 Secondary => True,
109 Tertiary => CPU >= Ivybridge);
110
111 type Valid_Per_Port is array (Port_Type) of Boolean;
112 type Valid_Per_GPU is array (CPU_Type) of Valid_Per_Port;
113 Valid_Port_GPU : Valid_Per_GPU :=
114 (Ironlake => Valid_Per_Port'
115 (Disabled => False,
116 Internal => Config.Internal_Display = LVDS,
117 others => True),
118 Sandybridge => Valid_Per_Port'
119 (Disabled => False,
120 Internal => Config.Internal_Display = LVDS,
121 others => True),
122 Ivybridge => Valid_Per_Port'
123 (Disabled => False,
124 Internal => Config.Internal_Display /= None,
125 others => True),
126 Haswell => Valid_Per_Port'
127 (Disabled => False,
128 Internal => Config.Internal_Display = DP,
129 Digital3 => CPU_Var = Normal,
130 DP3 => CPU_Var = Normal,
131 Analog => CPU_Var = Normal,
132 others => True),
133 Broadwell => Valid_Per_Port'
134 (Disabled => False,
135 Internal => Config.Internal_Display = DP,
136 Digital3 => CPU_Var = Normal,
137 DP3 => CPU_Var = Normal,
138 Analog => CPU_Var = Normal,
139 others => True),
140 Skylake => Valid_Per_Port'
141 (Disabled => False,
142 Internal => Config.Internal_Display = DP,
143 Analog => False,
144 others => True))
145 with
146 Part_Of => GMA.Config_State;
147 Valid_Port : Valid_Per_Port renames Valid_Port_GPU (CPU);
148
149 ----------------------------------------------------------------------------
150
151 type FDI_Per_Port is array (GPU_Port) of Boolean;
152 type FDI_Per_GPU is array (CPU_Type) of FDI_Per_Port;
153 FDI_GPU : constant FDI_Per_GPU :=
154 (Ironlake => FDI_Per_Port'
155 (DIGI_A => False, -- directly connected eDP
156 DIGI_B => True,
157 DIGI_C => True,
158 DIGI_D => True,
159 others => False),
160 Sandybridge => FDI_Per_Port'
161 (DIGI_A => False, -- directly connected eDP
162 DIGI_B => True,
163 DIGI_C => True,
164 DIGI_D => True,
165 others => False),
166 Ivybridge => FDI_Per_Port'
167 (DIGI_A => False, -- directly connected eDP
168 DIGI_B => True,
169 DIGI_C => True,
170 DIGI_D => True,
171 others => False),
172 Haswell => FDI_Per_Port'
173 (DIGI_A => False,
174 DIGI_B => False,
175 DIGI_C => False,
176 DIGI_D => False,
177 DIGI_E => True, -- VGA option through FDI
178 others => False),
179 Broadwell => FDI_Per_Port'
180 (DIGI_A => False,
181 DIGI_B => False,
182 DIGI_C => False,
183 DIGI_D => False,
184 DIGI_E => CPU_Var = Normal, -- VGA option through FDI
185 others => False),
186 Skylake => FDI_Per_Port'
187 (others => False));
188 FDI_Port : FDI_Per_Port renames FDI_GPU (CPU);
189
190 type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count;
191 FDI_Lane_Count : constant FDI_Lanes_Per_Port :=
192 (DIGI_D => DP_Lane_Count_2,
193 others =>
194 (if CPU in Ironlake .. Ivybridge then
195 DP_Lane_Count_4
196 else
197 DP_Lane_Count_2));
198
199 FDI_Training : constant FDI_Training_Type :=
200 (case CPU is
201 when Ironlake => Simple_Training,
202 when Sandybridge => Full_Training,
203 when others => Auto_Training);
204
205end HW.GFX.GMA.Config;