| Nico Huber | ab70886 | 2026-05-27 19:22:57 +0200 | [diff] [blame] | 1 | -- |
| 2 | -- Copyright (C) 2022 Google, LLC |
| 3 | -- |
| 4 | -- This program is free software; you can redistribute it and/or modify |
| 5 | -- it under the terms of the GNU General Public License as published by |
| 6 | -- the Free Software Foundation; either version 2 of the License, or |
| 7 | -- (at your option) any later version. |
| 8 | -- |
| 9 | -- This program is distributed in the hope that it will be useful, |
| 10 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | -- GNU General Public License for more details. |
| 13 | -- |
| 14 | |
| 15 | private package HW.GFX.GMA.Power_Domains is |
| 16 | |
| 17 | -- Comment lifted from i915: |
| 18 | -- XE_LPD Power Domains |
| 19 | -- |
| 20 | -- Previous platforms required that PW(n-1) be enabled before PW(n). That |
| 21 | -- dependency chain turns into a dependency tree on XE_LPD: |
| 22 | -- |
| 23 | -- PW0 |
| 24 | -- | |
| 25 | -- --PW1-- |
| 26 | -- / \ |
| 27 | -- PWA --PW2-- |
| 28 | -- / | \ |
| 29 | -- PWB PWC PWD |
| 30 | -- |
| 31 | -- Power wells must be enabled from top to bottom and disabled from bottom |
| 32 | -- to top. This allows pipes to be power gated independently. |
| 33 | |
| 34 | type Power_Domain is |
| 35 | (PW1, PWA, PW2, PWB, PWC, PWD, |
| 36 | -- order matters, bit positions for D & E replace USBC5 & 6 from TGL: |
| 37 | AUX_A, AUX_B, AUX_C, AUX_USBC1, AUX_USBC2, AUX_USBC3, AUX_USBC4, AUX_D, AUX_E, |
| 38 | DDI_A, DDI_B, DDI_C, DDI_USBC1, DDI_USBC2, DDI_USBC3, DDI_USBC4, DDI_D, DDI_E); |
| 39 | subtype Dynamic_Domain is Power_Domain range PWA .. DDI_E; |
| 40 | subtype PW_Domain is Power_Domain range PW1 .. PWD; |
| 41 | subtype Dynamic_Well is Power_Domain range PWA .. PWD; |
| 42 | subtype Port_Domain is Power_Domain range AUX_A .. DDI_E; |
| 43 | subtype DDI_Domain is Power_Domain range DDI_A .. DDI_E; |
| 44 | subtype DDI_PW2_Domain is Power_Domain range DDI_C .. DDI_E; |
| 45 | subtype DDI_USBC_Domain is Power_Domain range DDI_USBC1 .. DDI_USBC4; |
| 46 | subtype AUX_Domain is Power_Domain range AUX_A .. AUX_E; |
| 47 | subtype AUX_USBC_Domain is Power_Domain range AUX_USBC1 .. AUX_USBC4; |
| 48 | |
| 49 | ---------------------------------------------------------------------------- |
| 50 | |
| 51 | FUSE_STATUS_PGx_DIST_STATUS : constant array (PW_Domain) of Word32 := |
| 52 | (PW1 => 1 * 2 ** 26, |
| 53 | PW2 => 1 * 2 ** 25, |
| 54 | PWA => 1 * 2 ** 21, |
| 55 | PWB => 1 * 2 ** 20, |
| 56 | PWC => 1 * 2 ** 19, |
| 57 | PWD => 1 * 2 ** 18); |
| 58 | |
| 59 | ---------------------------------------------------------------------------- |
| 60 | |
| 61 | PW_State_Mask : constant array (PW_Domain) of Word32 := |
| 62 | (PW1 => 1 * 2 ** 0, |
| 63 | PW2 => 1 * 2 ** 2, |
| 64 | PWA => 1 * 2 ** 10, |
| 65 | PWB => 1 * 2 ** 12, |
| 66 | PWC => 1 * 2 ** 14, |
| 67 | PWD => 1 * 2 ** 16); |
| 68 | |
| 69 | ---------------------------------------------------------------------------- |
| 70 | |
| 71 | function To_GPU_Port (PD : Port_Domain) return GPU_Port |
| 72 | is |
| 73 | (case PD is |
| 74 | when DDI_A | AUX_A => DIGI_A, |
| 75 | when DDI_B | AUX_B => DIGI_B, |
| 76 | when DDI_C | AUX_C => DIGI_C, |
| 77 | when DDI_D | AUX_D => DIGI_D, |
| 78 | when DDI_E | AUX_E => DIGI_E, |
| 79 | when DDI_USBC1 | AUX_USBC1 => DDI_TC1, |
| 80 | when DDI_USBC2 | AUX_USBC2 => DDI_TC2, |
| 81 | when DDI_USBC3 | AUX_USBC3 => DDI_TC3, |
| 82 | when DDI_USBC4 | AUX_USBC4 => DDI_TC4); |
| 83 | |
| 84 | ---------------------------------------------------------------------------- |
| 85 | |
| 86 | function Need_PW (PW : Dynamic_Well; Configs : Pipe_Configs) return Boolean; |
| 87 | |
| 88 | procedure Power_Up (Port : Active_Port_Type; Success : out Boolean); |
| 89 | |
| 90 | end HW.GFX.GMA.Power_Domains; |