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review.sourcearcade.org / libgfxinit / 6f9a50dbaef0e3a36711b4348c58bc249e2cb486 / . / common / hw-gfx-gma-registers.ads
blob: 68763c81c2b3e523da135192c6e240c11dbfe75f [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
108 PORT_CLK_SEL_DDIA,
109 PORT_CLK_SEL_DDIB,
110 PORT_CLK_SEL_DDIC,
111 PORT_CLK_SEL_DDID,
112 PORT_CLK_SEL_DDIE,
113 TRANSA_CLK_SEL,
114 TRANSB_CLK_SEL,
115 TRANSC_CLK_SEL,
116 NDE_RSTWRN_OPT,
117 BLC_PWM_CPU_CTL2,
118 BLC_PWM_CPU_CTL,
119 HTOTAL_A,
120 HBLANK_A,
121 HSYNC_A,
122 VTOTAL_A,
123 VBLANK_A,
124 VSYNC_A,
125 PIPEASRC,
126 PIPE_VSYNCSHIFT_A,
127 PIPEA_DATA_M1,
128 PIPEA_DATA_N1,
129 PIPEA_LINK_M1,
130 PIPEA_LINK_N1,
131 FDI_TX_CTL_A,
132 PIPEA_DDI_FUNC_CTL,
133 PIPEA_MSA_MISC,
134 SRD_CTL_A,
135 SRD_STATUS_A,
136 HTOTAL_B,
137 HBLANK_B,
138 HSYNC_B,
139 VTOTAL_B,
140 VBLANK_B,
141 VSYNC_B,
142 PIPEBSRC,
143 PIPE_VSYNCSHIFT_B,
144 PIPEB_DATA_M1,
145 PIPEB_DATA_N1,
146 PIPEB_LINK_M1,
147 PIPEB_LINK_N1,
148 FDI_TX_CTL_B,
149 PIPEB_DDI_FUNC_CTL,
150 PIPEB_MSA_MISC,
151 SRD_CTL_B,
152 SRD_STATUS_B,
153 HTOTAL_C,
154 HBLANK_C,
155 HSYNC_C,
156 VTOTAL_C,
157 VBLANK_C,
158 VSYNC_C,
159 PIPECSRC,
160 PIPE_VSYNCSHIFT_C,
161 PIPEC_DATA_M1,
162 PIPEC_DATA_N1,
163 PIPEC_LINK_M1,
164 PIPEC_LINK_N1,
165 FDI_TX_CTL_C,
166 PIPEC_DDI_FUNC_CTL,
167 PIPEC_MSA_MISC,
168 SRD_CTL_C,
169 SRD_STATUS_C,
170 DDI_BUF_CTL_A,
171 DDI_AUX_CTL_A,
172 DDI_AUX_DATA_A_1,
173 DDI_AUX_DATA_A_2,
174 DDI_AUX_DATA_A_3,
175 DDI_AUX_DATA_A_4,
176 DDI_AUX_DATA_A_5,
177 DDI_AUX_MUTEX_A,
178 DP_TP_CTL_A,
179 DDI_BUF_CTL_B,
180 DDI_AUX_CTL_B,
181 DDI_AUX_DATA_B_1,
182 DDI_AUX_DATA_B_2,
183 DDI_AUX_DATA_B_3,
184 DDI_AUX_DATA_B_4,
185 DDI_AUX_DATA_B_5,
186 DDI_AUX_MUTEX_B,
187 DP_TP_CTL_B,
188 DP_TP_STATUS_B,
189 DDI_BUF_CTL_C,
190 DDI_AUX_CTL_C,
191 DDI_AUX_DATA_C_1,
192 DDI_AUX_DATA_C_2,
193 DDI_AUX_DATA_C_3,
194 DDI_AUX_DATA_C_4,
195 DDI_AUX_DATA_C_5,
196 DDI_AUX_MUTEX_C,
197 DP_TP_CTL_C,
198 DP_TP_STATUS_C,
199 DDI_BUF_CTL_D,
200 DDI_AUX_CTL_D,
201 DDI_AUX_DATA_D_1,
202 DDI_AUX_DATA_D_2,
203 DDI_AUX_DATA_D_3,
204 DDI_AUX_DATA_D_4,
205 DDI_AUX_DATA_D_5,
206 DDI_AUX_MUTEX_D,
207 DP_TP_CTL_D,
208 DP_TP_STATUS_D,
209 DDI_BUF_CTL_E,
210 DP_TP_CTL_E,
211 DP_TP_STATUS_E,
212 SRD_CTL,
213 SRD_STATUS,
214 AUD_VID_DID,
215 PFA_WIN_POS,
216 PFA_WIN_SZ,
217 PFA_CTL_1,
218 PS_WIN_POS_1_A,
219 PS_WIN_SZ_1_A,
220 PS_CTRL_1_A,
221 PS_WIN_POS_2_A,
222 PS_WIN_SZ_2_A,
223 PS_CTRL_2_A,
224 PFB_WIN_POS,
225 PFB_WIN_SZ,
226 PFB_CTL_1,
227 PS_WIN_POS_1_B,
228 PS_WIN_SZ_1_B,
229 PS_CTRL_1_B,
230 PS_WIN_POS_2_B,
231 PS_WIN_SZ_2_B,
232 PS_CTRL_2_B,
233 PFC_WIN_POS,
234 PFC_WIN_SZ,
235 PFC_CTL_1,
236 PS_WIN_POS_1_C,
237 PS_WIN_SZ_1_C,
238 PS_CTRL_1_C,
239 DPLL1_CFGR1,
240 DPLL1_CFGR2,
241 DPLL2_CFGR1,
242 DPLL2_CFGR2,
243 DPLL3_CFGR1,
244 DPLL3_CFGR2,
245 DPLL_CTRL1,
246 DPLL_CTRL2,
247 DPLL_STATUS,
248 HTOTAL_EDP,
249 HBLANK_EDP,
250 HSYNC_EDP,
251 VTOTAL_EDP,
252 VBLANK_EDP,
253 VSYNC_EDP,
254 PIPE_EDP_DATA_M1,
255 PIPE_EDP_DATA_N1,
256 PIPE_EDP_LINK_M1,
257 PIPE_EDP_LINK_N1,
258 PIPE_EDP_DDI_FUNC_CTL,
259 PIPE_EDP_MSA_MISC,
260 SRD_CTL_EDP,
261 SRD_STATUS_EDP,
262 PIPE_SCANLINE_A,
263 PIPEACONF,
264 PIPEAMISC,
265 PIPE_FRMCNT_A,
266 DSPACNTR,
267 DSPALINOFF,
268 DSPASTRIDE,
269 PLANE_POS_1_A,
270 PLANE_SIZE_1_A,
271 DSPASURF,
272 DSPATILEOFF,
273 PLANE_WM_1_A_0,
274 PLANE_WM_1_A_1,
275 PLANE_WM_1_A_2,
276 PLANE_WM_1_A_3,
277 PLANE_WM_1_A_4,
278 PLANE_WM_1_A_5,
279 PLANE_WM_1_A_6,
280 PLANE_WM_1_A_7,
281 PLANE_BUF_CFG_1_A,
282 SPACNTR,
283 PIPE_SCANLINE_B,
284 PIPEBCONF,
285 PIPEBMISC,
286 PIPE_FRMCNT_B,
287 DSPBCNTR,
288 DSPBLINOFF,
289 DSPBSTRIDE,
290 PLANE_POS_1_B,
291 PLANE_SIZE_1_B,
292 DSPBSURF,
293 DSPBTILEOFF,
294 PLANE_WM_1_B_0,
295 PLANE_WM_1_B_1,
296 PLANE_WM_1_B_2,
297 PLANE_WM_1_B_3,
298 PLANE_WM_1_B_4,
299 PLANE_WM_1_B_5,
300 PLANE_WM_1_B_6,
301 PLANE_WM_1_B_7,
302 PLANE_BUF_CFG_1_B,
303 SPBCNTR,
304 PIPE_SCANLINE_C,
305 PIPECCONF,
306 PIPECMISC,
307 PIPE_FRMCNT_C,
308 DSPCCNTR,
309 DSPCLINOFF,
310 DSPCSTRIDE,
311 PLANE_POS_1_C,
312 PLANE_SIZE_1_C,
313 DSPCSURF,
314 DSPCTILEOFF,
315 PLANE_WM_1_C_0,
316 PLANE_WM_1_C_1,
317 PLANE_WM_1_C_2,
318 PLANE_WM_1_C_3,
319 PLANE_WM_1_C_4,
320 PLANE_WM_1_C_5,
321 PLANE_WM_1_C_6,
322 PLANE_WM_1_C_7,
323 PLANE_BUF_CFG_1_C,
324 SPCCNTR,
325 PIPE_EDP_CONF,
326 PCH_FDI_CHICKEN_B_C,
327 QUIRK_C2004,
328 SFUSE_STRAP,
329 PCH_DSPCLK_GATE_D,
330 SDEISR,
331 SDEIMR,
332 SDEIIR,
333 SDEIER,
334 SHOTPLUG_CTL,
335 PCH_GMBUS0,
336 PCH_GMBUS1,
337 PCH_GMBUS2,
338 PCH_GMBUS3,
339 PCH_GMBUS4,
340 PCH_GMBUS5,
341 SBI_ADDR,
342 SBI_DATA,
343 SBI_CTL_STAT,
344 PCH_DPLL_A,
345 PCH_DPLL_B,
346 PCH_PIXCLK_GATE,
347 PCH_FPA0,
348 PCH_FPA1,
349 PCH_FPB0,
350 PCH_FPB1,
351 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]352 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]353 PCH_DPLL_SEL,
354 PCH_PP_STATUS,
355 PCH_PP_CONTROL,
356 PCH_PP_ON_DELAYS,
357 PCH_PP_OFF_DELAYS,
358 PCH_PP_DIVISOR,
359 BLC_PWM_PCH_CTL1,
360 BLC_PWM_PCH_CTL2,
361 TRANS_HTOTAL_A,
362 TRANS_HBLANK_A,
363 TRANS_HSYNC_A,
364 TRANS_VTOTAL_A,
365 TRANS_VBLANK_A,
366 TRANS_VSYNC_A,
367 TRANS_VSYNCSHIFT_A,
368 TRANSA_DATA_M1,
369 TRANSA_DATA_N1,
370 TRANSA_DP_LINK_M1,
371 TRANSA_DP_LINK_N1,
372 TRANS_DP_CTL_A,
373 TRANS_HTOTAL_B,
374 TRANS_HBLANK_B,
375 TRANS_HSYNC_B,
376 TRANS_VTOTAL_B,
377 TRANS_VBLANK_B,
378 TRANS_VSYNC_B,
379 TRANS_VSYNCSHIFT_B,
380 TRANSB_DATA_M1,
381 TRANSB_DATA_N1,
382 TRANSB_DP_LINK_M1,
383 TRANSB_DP_LINK_N1,
384 PCH_ADPA,
385 PCH_HDMIB,
386 PCH_HDMIC,
387 PCH_HDMID,
388 PCH_LVDS,
389 TRANS_DP_CTL_B,
390 TRANS_HTOTAL_C,
391 TRANS_HBLANK_C,
392 TRANS_HSYNC_C,
393 TRANS_VTOTAL_C,
394 TRANS_VBLANK_C,
395 TRANS_VSYNC_C,
396 TRANS_VSYNCSHIFT_C,
397 TRANSC_DATA_M1,
398 TRANSC_DATA_N1,
399 TRANSC_DP_LINK_M1,
400 TRANSC_DP_LINK_N1,
401 TRANS_DP_CTL_C,
402 PCH_DP_B,
403 PCH_DP_AUX_CTL_B,
404 PCH_DP_AUX_DATA_B_1,
405 PCH_DP_AUX_DATA_B_2,
406 PCH_DP_AUX_DATA_B_3,
407 PCH_DP_AUX_DATA_B_4,
408 PCH_DP_AUX_DATA_B_5,
409 PCH_DP_C,
410 PCH_DP_AUX_CTL_C,
411 PCH_DP_AUX_DATA_C_1,
412 PCH_DP_AUX_DATA_C_2,
413 PCH_DP_AUX_DATA_C_3,
414 PCH_DP_AUX_DATA_C_4,
415 PCH_DP_AUX_DATA_C_5,
416 PCH_DP_D,
417 PCH_DP_AUX_CTL_D,
418 PCH_DP_AUX_DATA_D_1,
419 PCH_DP_AUX_DATA_D_2,
420 PCH_DP_AUX_DATA_D_3,
421 PCH_DP_AUX_DATA_D_4,
422 PCH_DP_AUX_DATA_D_5,
423 AUD_CONFIG_A,
424 PCH_AUD_VID_DID,
425 AUD_HDMIW_HDMIEDID_A,
426 AUD_CNTL_ST_A,
427 AUD_CNTRL_ST2,
428 AUD_CONFIG_B,
429 AUD_HDMIW_HDMIEDID_B,
430 AUD_CNTL_ST_B,
431 AUD_CONFIG_C,
432 AUD_HDMIW_HDMIEDID_C,
433 AUD_CNTL_ST_C,
434 TRANSACONF,
435 FDI_RXA_CTL,
436 FDI_RX_MISC_A,
437 FDI_RXA_IIR,
438 FDI_RXA_IMR,
439 FDI_RXA_TUSIZE1,
440 QUIRK_F0060,
441 TRANSA_CHICKEN2,
442 TRANSBCONF,
443 FDI_RXB_CTL,
444 FDI_RX_MISC_B,
445 FDI_RXB_IIR,
446 FDI_RXB_IMR,
447 FDI_RXB_TUSIZE1,
448 QUIRK_F1060,
449 TRANSB_CHICKEN2,
450 TRANSCCONF,
451 FDI_RXC_CTL,
452 FDI_RX_MISC_C,
453 FDI_RXC_IIR,
454 FDI_RXC_IMR,
455 FDI_RXC_TUSIZE1,
456 QUIRK_F2060,
457 TRANSC_CHICKEN2,
458 GT_MAILBOX,
459 GT_MAILBOX_DATA,
460 GT_MAILBOX_DATA_1);
461
462 pragma Warnings
463 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
464 Reason => "TODO: Should it matter?");
465 pragma Keep_Names (Registers_Invalid_Index);
466 pragma Warnings
467 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
468
469 Register_Width : constant := 4;
470
471 for Registers_Invalid_Index use
472 (Invalid_Register => 0,
473
474 ---------------------------------------------------------------------------
475 -- Pipe A registers
476 ---------------------------------------------------------------------------
477
478 -- pipe timing registers
479
480 HTOTAL_A => 16#06_0000# / Register_Width,
481 HBLANK_A => 16#06_0004# / Register_Width,
482 HSYNC_A => 16#06_0008# / Register_Width,
483 VTOTAL_A => 16#06_000c# / Register_Width,
484 VBLANK_A => 16#06_0010# / Register_Width,
485 VSYNC_A => 16#06_0014# / Register_Width,
486 PIPEASRC => 16#06_001c# / Register_Width,
487 PIPEACONF => 16#07_0008# / Register_Width,
488 PIPEAMISC => 16#07_0030# / Register_Width,
489 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
490 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
491 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
492 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
493 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
494 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
495 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
496 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
497 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
498 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
499 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
500 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
501 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
502 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
503 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
504 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
505
506 -- PCH sideband interface registers
507 SBI_ADDR => 16#0c_6000# / Register_Width,
508 SBI_DATA => 16#0c_6004# / Register_Width,
509 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
510
511 -- clock registers
512 PCH_DPLL_A => 16#0c_6014# / Register_Width,
513 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
514 PCH_FPA0 => 16#0c_6040# / Register_Width,
515 PCH_FPA1 => 16#0c_6044# / Register_Width,
516
517 -- panel fitter
518 PFA_CTL_1 => 16#06_8080# / Register_Width,
519 PFA_WIN_POS => 16#06_8070# / Register_Width,
520 PFA_WIN_SZ => 16#06_8074# / Register_Width,
521 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
522 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
523 PS_CTRL_1_A => 16#06_8180# / Register_Width,
524 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
525 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
526 PS_CTRL_2_A => 16#06_8280# / Register_Width,
527
528 -- display control
529 DSPACNTR => 16#07_0180# / Register_Width,
530 DSPALINOFF => 16#07_0184# / Register_Width,
531 DSPASTRIDE => 16#07_0188# / Register_Width,
532 PLANE_POS_1_A => 16#07_018c# / Register_Width,
533 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
534 DSPASURF => 16#07_019c# / Register_Width,
535 DSPATILEOFF => 16#07_01a4# / Register_Width,
536
537 -- sprite control
538 SPACNTR => 16#07_0280# / Register_Width,
539
540 -- FDI and PCH transcoder control
541 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
542 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
543 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
544 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
545 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
546 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
547 TRANSACONF => 16#0f_0008# / Register_Width,
548 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
549
550 -- watermark registers
551 WM_LINETIME_A => 16#04_5270# / Register_Width,
552 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
553 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
554 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
555 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
556 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
557 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
558 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
559 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
560 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
561
562 -- CPU transcoder clock select
563 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
564
565 ---------------------------------------------------------------------------
566 -- Pipe B registers
567 ---------------------------------------------------------------------------
568
569 -- pipe timing registers
570
571 HTOTAL_B => 16#06_1000# / Register_Width,
572 HBLANK_B => 16#06_1004# / Register_Width,
573 HSYNC_B => 16#06_1008# / Register_Width,
574 VTOTAL_B => 16#06_100c# / Register_Width,
575 VBLANK_B => 16#06_1010# / Register_Width,
576 VSYNC_B => 16#06_1014# / Register_Width,
577 PIPEBSRC => 16#06_101c# / Register_Width,
578 PIPEBCONF => 16#07_1008# / Register_Width,
579 PIPEBMISC => 16#07_1030# / Register_Width,
580 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
581 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
582 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
583 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
584 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
585 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
586 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
587 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
588 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
589 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
590 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
591 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
592 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
593 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
594 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
595 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
596
597 -- clock registers
598 PCH_DPLL_B => 16#0c_6018# / Register_Width,
599 PCH_FPB0 => 16#0c_6048# / Register_Width,
600 PCH_FPB1 => 16#0c_604c# / Register_Width,
601
602 -- panel fitter
603 PFB_CTL_1 => 16#06_8880# / Register_Width,
604 PFB_WIN_POS => 16#06_8870# / Register_Width,
605 PFB_WIN_SZ => 16#06_8874# / Register_Width,
606 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
607 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
608 PS_CTRL_1_B => 16#06_8980# / Register_Width,
609 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
610 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
611 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
612
613 -- display control
614 DSPBCNTR => 16#07_1180# / Register_Width,
615 DSPBLINOFF => 16#07_1184# / Register_Width,
616 DSPBSTRIDE => 16#07_1188# / Register_Width,
617 PLANE_POS_1_B => 16#07_118c# / Register_Width,
618 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
619 DSPBSURF => 16#07_119c# / Register_Width,
620 DSPBTILEOFF => 16#07_11a4# / Register_Width,
621
622 -- sprite control
623 SPBCNTR => 16#07_1280# / Register_Width,
624
625 -- FDI and PCH transcoder control
626 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
627 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
628 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
629 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
630 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
631 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
632 TRANSBCONF => 16#0f_1008# / Register_Width,
633 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
634
635 -- watermark registers
636 WM_LINETIME_B => 16#04_5274# / Register_Width,
637 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
638 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
639 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
640 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
641 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
642 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
643 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
644 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
645 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
646
647 -- CPU transcoder clock select
648 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
649
650 ---------------------------------------------------------------------------
651 -- Pipe C registers
652 ---------------------------------------------------------------------------
653
654 -- pipe timing registers
655
656 HTOTAL_C => 16#06_2000# / Register_Width,
657 HBLANK_C => 16#06_2004# / Register_Width,
658 HSYNC_C => 16#06_2008# / Register_Width,
659 VTOTAL_C => 16#06_200c# / Register_Width,
660 VBLANK_C => 16#06_2010# / Register_Width,
661 VSYNC_C => 16#06_2014# / Register_Width,
662 PIPECSRC => 16#06_201c# / Register_Width,
663 PIPECCONF => 16#07_2008# / Register_Width,
664 PIPECMISC => 16#07_2030# / Register_Width,
665 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
666 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
667 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
668 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
669 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
670 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
671 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
672 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
673 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
674 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
675 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
676 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
677 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
678 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
679 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
680 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
681
682 -- panel fitter
683 PFC_CTL_1 => 16#06_9080# / Register_Width,
684 PFC_WIN_POS => 16#06_9070# / Register_Width,
685 PFC_WIN_SZ => 16#06_9074# / Register_Width,
686 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
687 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
688 PS_CTRL_1_C => 16#06_9180# / Register_Width,
689
690 -- display control
691 DSPCCNTR => 16#07_2180# / Register_Width,
692 DSPCLINOFF => 16#07_2184# / Register_Width,
693 DSPCSTRIDE => 16#07_2188# / Register_Width,
694 PLANE_POS_1_C => 16#07_218c# / Register_Width,
695 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
696 DSPCSURF => 16#07_219c# / Register_Width,
697 DSPCTILEOFF => 16#07_21a4# / Register_Width,
698
699 -- sprite control
700 SPCCNTR => 16#07_2280# / Register_Width,
701
702 -- PCH transcoder control
703 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
704 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
705 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
706 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
707 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
708 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
709 TRANSCCONF => 16#0f_2008# / Register_Width,
710 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
711
712 -- watermark registers
713 WM_LINETIME_C => 16#04_5278# / Register_Width,
714 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
715 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
716 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
717 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
718 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
719 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
720 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
721 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
722 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
723
724 -- CPU transcoder clock select
725 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
726
727 ---------------------------------------------------------------------------
728 -- Pipe EDP registers
729 ---------------------------------------------------------------------------
730
731 -- pipe timing registers
732
733 HTOTAL_EDP => 16#06_f000# / Register_Width,
734 HBLANK_EDP => 16#06_f004# / Register_Width,
735 HSYNC_EDP => 16#06_f008# / Register_Width,
736 VTOTAL_EDP => 16#06_f00c# / Register_Width,
737 VBLANK_EDP => 16#06_f010# / Register_Width,
738 VSYNC_EDP => 16#06_f014# / Register_Width,
739 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
740 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
741 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
742 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
743 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
744 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
745 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
746
747 -- PSR registers
748 SRD_CTL => 16#06_4800# / Register_Width,
749 SRD_CTL_A => 16#06_0800# / Register_Width,
750 SRD_CTL_B => 16#06_1800# / Register_Width,
751 SRD_CTL_C => 16#06_2800# / Register_Width,
752 SRD_CTL_EDP => 16#06_f800# / Register_Width,
753 SRD_STATUS => 16#06_4840# / Register_Width,
754 SRD_STATUS_A => 16#06_0840# / Register_Width,
755 SRD_STATUS_B => 16#06_1840# / Register_Width,
756 SRD_STATUS_C => 16#06_2840# / Register_Width,
757 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
758
759 -- DDI registers
760 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
761 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
762 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
763 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
764 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
765 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
766 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
767 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
768 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
769 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
770 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
771 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
772 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
773 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
774 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
775 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
776 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
777 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
778 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
779 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
780 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
781 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
782 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
783 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
784 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
785 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
786 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
787 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
788 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
789 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
790 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
791 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
792 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
793 DP_TP_CTL_A => 16#06_4040# / Register_Width,
794 DP_TP_CTL_B => 16#06_4140# / Register_Width,
795 DP_TP_CTL_C => 16#06_4240# / Register_Width,
796 DP_TP_CTL_D => 16#06_4340# / Register_Width,
797 DP_TP_CTL_E => 16#06_4440# / Register_Width,
798 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
799 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
800 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
801 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
802 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
803 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
804 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
805 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
806 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
807
808 -- Skylake DPLL registers
809 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
810 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
811 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
812 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
813 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
814 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
815 DPLL_CTRL1 => 16#06_c058# / Register_Width,
816 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
817 DPLL_STATUS => 16#06_c060# / Register_Width,
818
819 -- CD CLK register
820 CDCLK_CTL => 16#04_6000# / Register_Width,
821
822 -- Skylake LCPLL registers
823 LCPLL1_CTL => 16#04_6010# / Register_Width,
824 LCPLL2_CTL => 16#04_6014# / Register_Width,
825
826 -- SPLL register
827 SPLL_CTL => 16#04_6020# / Register_Width,
828
829 -- WRPLL registers
830 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
831 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
832
833 -- Power Down Well registers
834 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
835 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
836 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
837 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
838 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
839 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
840
841 -- class Panel registers
842 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
843 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
844 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
845 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
846 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
847 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
848 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
849
850 -- PCH LVDS Connector Registers
851 PCH_LVDS => 16#0e_1180# / Register_Width,
852
853 -- PCH ADPA Connector Registers
854 PCH_ADPA => 16#0e_1100# / Register_Width,
855
856 -- PCH HDMIB Connector Registers
857 PCH_HDMIB => 16#0e_1140# / Register_Width,
858
859 -- PCH HDMIC Connector Registers
860 PCH_HDMIC => 16#0e_1150# / Register_Width,
861
862 -- PCH HDMID Connector Registers
863 PCH_HDMID => 16#0e_1160# / Register_Width,
864
865 -- Intel Registers
866 VGACNTRL => 16#04_1000# / Register_Width,
867 FUSE_STATUS => 16#04_2000# / Register_Width,
868 FBA_CFB_BASE => 16#04_3200# / Register_Width,
869 IPS_CTL => 16#04_3408# / Register_Width,
870 ARB_CTL => 16#04_5000# / Register_Width,
871 DBUF_CTL => 16#04_5008# / Register_Width,
872 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
873 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
874 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
875 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
876 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
877 GT_MAILBOX => 16#13_8124# / Register_Width,
878 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
879 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
880
881 PCH_DP_B => 16#0e_4100# / Register_Width,
882 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
883 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
884 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
885 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
886 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
887 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
888 PCH_DP_C => 16#0e_4200# / Register_Width,
889 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
890 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
891 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
892 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
893 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
894 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
895 PCH_DP_D => 16#0e_4300# / Register_Width,
896 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
897 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
898 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
899 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
900 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
901 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
902
903 -- watermark registers
904 WM1_LP_ILK => 16#04_5108# / Register_Width,
905 WM2_LP_ILK => 16#04_510c# / Register_Width,
906 WM3_LP_ILK => 16#04_5110# / Register_Width,
907
908 -- audio VID/DID
909 AUD_VID_DID => 16#06_5020# / Register_Width,
910 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
911
912 -- interrupt registers
913 DEISR => 16#04_4000# / Register_Width,
914 DEIMR => 16#04_4004# / Register_Width,
915 DEIIR => 16#04_4008# / Register_Width,
916 DEIER => 16#04_400c# / Register_Width,
917 GTISR => 16#04_4010# / Register_Width,
918 GTIMR => 16#04_4014# / Register_Width,
919 GTIIR => 16#04_4018# / Register_Width,
920 GTIER => 16#04_401c# / Register_Width,
921 SDEISR => 16#0c_4000# / Register_Width,
922 SDEIMR => 16#0c_4004# / Register_Width,
923 SDEIIR => 16#0c_4008# / Register_Width,
924 SDEIER => 16#0c_400c# / Register_Width,
925
926 -- I2C stuff
927 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
928 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
929 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
930 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
931 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
932 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
933
934 -- clock gating -- maybe have to touch this
935 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
936 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
937 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
938
939 -- hotplug and initial detection
940 HOTPLUG_CTL => 16#04_4030# / Register_Width,
941 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
942 SFUSE_STRAP => 16#0c_2014# / Register_Width,
943
944 -- Render Engine Command Streamer
945 ARB_MODE => 16#00_4030# / Register_Width,
946 HWS_PGA => 16#00_4080# / Register_Width,
947 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
948 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
949 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
950 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
951 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
952 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
953 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
954 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
955 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
956 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
957 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
958 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
959 MI_MODE => 16#00_209c# / Register_Width,
960 INSTPM => 16#00_20c0# / Register_Width,
961 GAB_CTL_REG => 16#02_4000# / Register_Width,
962 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
963 PP_DCLV_LOW => 16#00_2228# / Register_Width,
964 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
965 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
966 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
967 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]968 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]969 UCGCTL1 => 16#00_9400# / Register_Width,
970 UCGCTL2 => 16#00_9404# / Register_Width,
971 MBCTL => 16#00_907c# / Register_Width,
972 HWSTAM => 16#00_2098# / Register_Width,
973 VCS_HWSTAM => 16#01_2098# / Register_Width,
974 BCS_HWSTAM => 16#02_2098# / Register_Width,
975 IIR => 16#04_4028# / Register_Width,
976 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
977 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
978 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
979 FBC_CTL => 16#04_3208# / Register_Width,
980 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
981 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
982 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
983 WM_PIPE_A => 16#04_5100# / Register_Width,
984 WM_PIPE_B => 16#04_5104# / Register_Width,
985 WM_PIPE_C => 16#04_5200# / Register_Width,
986 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
987 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
988 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
989 GFX_MODE => 16#00_2520# / Register_Width,
990 CACHE_MODE_0 => 16#00_2120# / Register_Width,
991 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
992 CTX_SIZE => 16#00_21a0# / Register_Width,
993 GAC_ECO_BITS => 16#01_4090# / Register_Width,
994 GAM_ECOCHK => 16#00_4090# / Register_Width,
995 QUIRK_02084 => 16#00_2084# / Register_Width,
996 QUIRK_02090 => 16#00_2090# / Register_Width,
997 GT_MODE => 16#00_20d0# / Register_Width,
998 QUIRK_F0060 => 16#0f_0060# / Register_Width,
999 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1000 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1001 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1002 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1003 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1004 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1005 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1006 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1007 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1008 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1009 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1010 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1011 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1012 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1013 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1014 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1015 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1016 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1017 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1018 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1019
1020 subtype Registers_Index is Registers_Invalid_Index range
1021 Registers_Invalid_Index'Succ (Invalid_Register) ..
1022 Registers_Invalid_Index'Last;
1023
1024 -- aliased registers
1025 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1026 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1027 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1028 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1029 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1030 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1031 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1032 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1033
1034 ---------------------------------------------------------------------------
1035
1036 Default_Timeout_MS : constant := 10;
1037
1038 ---------------------------------------------------------------------------
1039
1040 procedure Posting_Read
1041 (Register : in Registers_Index)
1042 with
1043 Global => (In_Out => Register_State),
1044 Depends => (Register_State =>+ (Register)),
1045 Pre => True,
1046 Post => True;
1047
1048 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1049 Reason => "Only used on debugging path");
1050 procedure Read
1051 (Register : in Registers_Index;
1052 Value : out Word32;
1053 Verbose : in Boolean := True)
1054 with
1055 Global => (In_Out => Register_State),
1056 Depends => ((Value, Register_State) => (Register, Register_State),
1057 null => Verbose),
1058 Pre => True,
1059 Post => True;
1060 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1061
1062 procedure Write
1063 (Register : Registers_Index;
1064 Value : Word32)
1065 with
1066 Global => (In_Out => Register_State),
1067 Depends => (Register_State => (Register, Register_State, Value)),
1068 Pre => True,
1069 Post => True;
1070
1071 procedure Is_Set_Mask
1072 (Register : in Registers_Index;
1073 Mask : in Word32;
1074 Result : out Boolean);
1075
1076 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1077 Reason => "Only used on debugging path");
1078 procedure Wait_Set_Mask
1079 (Register : Registers_Index;
1080 Mask : Word32;
1081 TOut_MS : Natural := Default_Timeout_MS;
1082 Verbose : Boolean := False);
1083
1084 procedure Wait_Unset_Mask
1085 (Register : Registers_Index;
1086 Mask : Word32;
1087 TOut_MS : Natural := Default_Timeout_MS;
1088 Verbose : Boolean := False);
1089 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1090
1091 procedure Set_Mask
1092 (Register : Registers_Index;
1093 Mask : Word32);
1094
1095 procedure Unset_Mask
1096 (Register : Registers_Index;
1097 Mask : Word32);
1098
1099 procedure Unset_And_Set_Mask
1100 (Register : Registers_Index;
1101 Mask_Unset : Word32;
1102 Mask_Set : Word32);
1103
1104 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1105 procedure Write_GTT
1106 (GTT_Page : GTT_Range;
1107 Device_Address : GTT_Address_Type;
1108 Valid : Boolean)
1109 with
1110 Global => (In_Out => GTT_State),
1111 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1112 Pre => True,
1113 Post => True;
1114 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1115
1116 procedure Set_Register_Base (Base : Word64)
1117 with
1118 Global => (Output => Address_State),
1119 Depends => (Address_State => Base),
1120 Pre => True,
1121 Post => True;
1122
1123end HW.GFX.GMA.Registers;