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review.sourcearcade.org / libgfxinit / 68deeb44d0db3cd28c82887396fb7f385e208b3b / . / common / i945 / hw-gfx-gma-plls.adb
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Arthur Heymans960e2392026-03-03 19:45:24 +0100[diff] [blame]1--
2-- Copyright (C) 2026 Arthur Heymans <arthur@aheymans.xyz>
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with HW.Time;
16with HW.GFX.GMA.Config;
17with HW.GFX.GMA.Registers;
18
19with HW.Debug;
20with GNAT.Source_Info;
21
22package body HW.GFX.GMA.PLLs
23with
24 Refined_State => (State => PLLs)
25is
26
27 Debug_Clocks : constant Boolean := False;
28
29 type Count_Range is new Natural range 0 .. 2;
30
31 type PLL_State is record
32 Use_Count : Count_Range;
33 Mode : Mode_Type;
34 end record;
35
36 type PLL_State_Array is array (DPLLs) of PLL_State;
37
38 PLLs : PLL_State_Array;
39
40 ----------------------------------------------------------------------------
41
42 -- i945 PLL limits use "actual" divider values (register_value + 2).
43 -- Linux kernel i9xx limits (register values):
44 -- N: 1..6, M1: 8..18, M2: 3..7
45 -- Actual values (register + 2):
46 -- N: 3..8, M1: 10..20, M2: 5..9
47 -- M = 5 * M1 + M2, range 70..120
48 -- VCO = ref_clk * M / N, range 1400..2800 MHz
49 -- Reference clock: 96 MHz
50
51 subtype N_Range is Int64 range 3 .. 8;
52 subtype M_Range is Int64 range 70 .. 120;
53 subtype M1_Range is Int64 range 10 .. 20;
54 subtype M2_Range is Int64 range 5 .. 9;
55 subtype P_Range is Int64 range 5 .. 98;
56 subtype P1_Range is Int64 range 1 .. 8;
57 subtype P2_Range is Int64 range 5 .. 14;
58 subtype VCO_Range is Int64 range 1400000000 .. 2800000000;
59 subtype Clock_Range is HW.GFX.Frequency_Type;
60
61 type Clock_Type is
62 record
63 N : N_Range;
64 M1 : M1_Range;
65 M2 : M2_Range;
66 P1 : P1_Range;
67 P2 : P2_Range;
68 M : M_Range;
69 P : P_Range;
70 VCO : VCO_Range;
71 Reference_Clock : Clock_Range;
72 Dotclock : Clock_Range;
73 end record;
74
75 Invalid_Clock : constant Clock_Type := Clock_Type'
76 (N => N_Range'Last,
77 M1 => M1_Range'Last,
78 M2 => M2_Range'Last,
79 P1 => P1_Range'Last,
80 P2 => P2_Range'Last,
81 Reference_Clock => Clock_Range'Last,
82 M => M_Range'Last,
83 P => P_Range'Last,
84 VCO => VCO_Range'Last,
85 Dotclock => Clock_Range'Last);
86
87 type Limits_Type is
88 record
89 N_Lower : N_Range;
90 N_Upper : N_Range;
91 M_Lower : M_Range;
92 M_Upper : M_Range;
93 M1_Lower : M1_Range;
94 M1_Upper : M1_Range;
95 M2_Lower : M2_Range;
96 M2_Upper : M2_Range;
97 P_Lower : P_Range;
98 P_Upper : P_Range;
99 P1_Lower : P1_Range;
100 P1_Upper : P1_Range;
101 P2_Fast : P2_Range;
102 P2_Slow : P2_Range;
103 P2_Threshold : Clock_Range;
104 VCO_Lower : VCO_Range;
105 VCO_Upper : VCO_Range;
106 end record;
107
108 -- i9xx LVDS limits (from Linux intel_limits_i9xx_lvds)
109 LVDS_Limits : constant Limits_Type := Limits_Type'
110 (N_Lower => 3, N_Upper => 8,
111 M_Lower => 70, M_Upper => 120,
112 M1_Lower => 10, M1_Upper => 20,
113 M2_Lower => 5, M2_Upper => 9,
114 P_Lower => 7, P_Upper => 98,
115 P1_Lower => 1, P1_Upper => 8,
116 P2_Fast => 7, P2_Slow => 14,
117 P2_Threshold => 112_000_000,
118 VCO_Lower => 1_400_000_000, VCO_Upper => 2_800_000_000);
119
120 -- i9xx SDVO/DAC limits (from Linux intel_limits_i9xx_sdvo)
121 SDVO_DAC_Limits : constant Limits_Type := Limits_Type'
122 (N_Lower => 3, N_Upper => 8,
123 M_Lower => 70, M_Upper => 120,
124 M1_Lower => 10, M1_Upper => 20,
125 M2_Lower => 5, M2_Upper => 9,
126 P_Lower => 5, P_Upper => 80,
127 P1_Lower => 1, P1_Upper => 8,
128 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
129 P2_Fast => 5, P2_Slow => 10,
130 P2_Threshold => 200_000_000,
131 VCO_Lower => 1_400_000_000, VCO_Upper => 2_800_000_000);
132
133 ----------------------------------------------------------------------------
134
135 type Regs is array (DPLLs) of Registers.Registers_Index;
136
137 DPLL : constant Regs := Regs'(Registers.GMCH_DPLL_A, Registers.GMCH_DPLL_B);
138 DPLL_VCO_ENABLE : constant := 1 * 2 ** 31;
139 DPLL_VGA_MODE_DIS : constant := 1 * 2 ** 28;
140 DPLL_P2_10_OR_14 : constant := 0 * 2 ** 24;
141 DPLL_P2_5_OR_7 : constant := 1 * 2 ** 24;
142 DPLL_P1_DIVIDER_SHIFT : constant := 16;
143 DPLL_SDVOCLK : constant := 2 * 2 ** 13;
144
145 -- i945 does not use DPLL_PULSE_PHASE (bits 12:9, Gen4+ only)
146 -- i945 uses DVO_2X_MODE (bit 30) for SDVO outputs (same bit as
147 -- DPLL_SDVO_HIGH_SPEED on Gen4+)
148 DPLL_DVO_2X_MODE : constant := 1 * 2 ** 30;
149 DPLL_MODE_LVDS : constant := 2 * 2 ** 26;
150 DPLL_MODE_DAC : constant := 1 * 2 ** 26;
151 DPLL_DREFCLK : constant := 0 * 2 ** 13;
152 DPLL_SSC : constant := 3 * 2 ** 13;
153
154 MODE_DPLL_DAC : constant Word32 := Word32'
155 (DPLL_MODE_DAC or DPLL_DREFCLK);
156
157 MODE_DPLL_SDVO : constant Word32 := Word32'
158 (DPLL_MODE_DAC or DPLL_DREFCLK or DPLL_DVO_2X_MODE);
159
160 MODE_DPLL_LVDS : constant Word32 := Word32'
161 (DPLL_MODE_LVDS or DPLL_SSC);
162
163 type DPLL_Mode_Array is array (Display_Type) of Word32;
164
165 DPLL_Mode : constant DPLL_Mode_Array := DPLL_Mode_Array'
166 (LVDS => MODE_DPLL_LVDS,
167 VGA => MODE_DPLL_DAC,
168 HDMI => MODE_DPLL_SDVO, -- SDVO outputs use HDMI display type
169 Others => MODE_DPLL_SDVO);
170
171 FP0 : constant Regs := Regs'(Registers.GMCH_FPA0, Registers.GMCH_FPB0);
172 FP1 : constant Regs := Regs'(Registers.GMCH_FPA1, Registers.GMCH_FPB1);
173 FP_N_SHIFT : constant := 16;
174 FP_M1_SHIFT : constant := 8;
175 FP_M2_SHIFT : constant := 0;
176
177 ----------------------------------------------------------------------------
178
179 procedure Verify_Parameters
180 (N : in N_Range;
181 M1 : in M1_Range;
182 M2 : in M2_Range;
183 P1 : in P1_Range;
184 P2 : in P2_Range;
185 Reference_Clock : in Clock_Range;
186 Current_Limits : in Limits_Type;
187 Result : out Clock_Type;
188 Valid : out Boolean)
189 with
190 Global => null,
191 Pre => True,
192 Post => True
193 is
194 M : Int64;
195 P : Int64;
196 VCO : Int64;
197 Dotclock : Int64;
198 begin
199 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
200
201 M := 5 * M1 + M2;
202 P := P1 * P2;
203 VCO := (Int64 (Reference_Clock) * M) / N;
204 Dotclock := VCO / P;
205
206 pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range."));
207 pragma Debug (Debug_Clocks and (Current_Limits.P2_Fast /= P2 and P2 /= Current_Limits.P2_Slow ), Debug.Put_Line ("P2 out of range."));
208 pragma Debug (Debug_Clocks and not (Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper ), Debug.Put_Line ("P out of range."));
209 pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range."));
210 pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range."));
211 pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper ), Debug.Put_Line ("N out of range."));
212 pragma Debug (Debug_Clocks and not (Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper ), Debug.Put_Line ("M out of range."));
213 pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range."));
214
215 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Line ("Dotclock too low."));
216 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Int64 (Dotclock));
217 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.New_Line);
218
219 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Line ("Dotclock too high."));
220 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Int64 (Dotclock));
221 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.New_Line);
222
223 Valid :=
224 Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper and
225 (Current_Limits.P2_Fast = P2 or P2 = Current_Limits.P2_Slow) and
226 Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper and
227 Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper and
228 Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper and
229 Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper and
230 Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper and
231 Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and
232 Int64 (Clock_Range'First) <= Dotclock and
233 Dotclock <= Int64 (Clock_Range'Last);
234
235 if Valid
236 then
237 Result := Clock_Type'
238 (N => N,
239 M1 => M1,
240 M2 => M2,
241 P1 => P1,
242 P2 => P2,
243 Reference_Clock => Reference_Clock,
244 M => M,
245 P => P,
246 VCO => VCO,
247 Dotclock => Clock_Range (Dotclock));
248 else
249 Result := Invalid_Clock;
250 end if;
251
252 end Verify_Parameters;
253
254 procedure Calculate_Clock_Parameters
255 (Display : in Display_Type;
256 Target_Dotclock : in Clock_Range;
257 Reference_Clock : in Clock_Range;
258 Best_Clock : out Clock_Type;
259 Valid : out Boolean)
260 with
261 Global => null,
262 Pre => True,
263 Post => True
264 is
265 Limits : constant Limits_Type :=
266 (case Display is
267 when LVDS => LVDS_Limits,
268 when others => SDVO_DAC_Limits);
269
270 P2 : P2_Range;
271 Best_Delta : Int64 := Int64'Last;
272 Current_Delta : Int64;
273 Current_Clock : Clock_Type;
274 Registers_Valid : Boolean;
275 begin
276 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
277
278 Valid := False;
279 Best_Clock := Invalid_Clock;
280
281 if Target_Dotclock <= Limits.P2_Threshold then
282 P2 := Limits.P2_Slow;
283 else
284 P2 := Limits.P2_Fast;
285 end if;
286
287 for N in N_Range range Limits.N_Lower .. Limits.N_Upper
288 loop
289 -- reverse loops as hardware prefers higher values
290 for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
291 loop
292 pragma Loop_Invariant (True);
293 for M2 in reverse M2_Range range Limits.M2_Lower .. Int64'Min (Limits.M2_Upper, M1)
294 loop
295 pragma Loop_Invariant (True);
296 for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
297 loop
298 Verify_Parameters
299 (N => N,
300 M1 => M1,
301 M2 => M2,
302 P1 => P1,
303 P2 => P2,
304 Reference_Clock => Reference_Clock,
305 Current_Limits => Limits,
306 Result => Current_Clock,
307 Valid => Registers_Valid);
308
309 if Registers_Valid
310 then
311 if Current_Clock.Dotclock > Target_Dotclock
312 then
313 Current_Delta := Current_Clock.Dotclock - Target_Dotclock;
314 else
315 Current_Delta := Target_Dotclock - Current_Clock.Dotclock;
316 end if;
317
318 if Current_Delta < Best_Delta
319 then
320 Best_Delta := Current_Delta;
321 Best_Clock := Current_Clock;
322 Valid := True;
323 end if;
324
325 pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: "));
326 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock));
327 pragma Debug (Debug_Clocks, Debug.Put ("/"));
328 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock));
329 pragma Debug (Debug_Clocks, Debug.Put ("/"));
330 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta));
331 pragma Debug (Debug_Clocks, Debug.Put_Line ("."));
332
333 end if;
334 end loop;
335 end loop;
336 end loop;
337 end loop;
338
339 pragma Debug (Valid, Debug.Put_Line ("Valid clock found."));
340 pragma Debug (Valid, Debug.Put ("Best/Target/Delta: "));
341 pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock));
342 pragma Debug (Valid, Debug.Put ("/"));
343 pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock));
344 pragma Debug (Valid, Debug.Put ("/"));
345 pragma Debug (Valid, Debug.Put_Int64 (Best_Delta));
346 pragma Debug (Valid, Debug.Put_Line ("."));
347 pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
348
349 end Calculate_Clock_Parameters;
350
351 procedure Program_DPLL
352 (PLL : DPLLs;
353 Display : Display_Type;
354 Clk : Clock_Type)
355 with
356 Global => (In_Out => Registers.Register_State),
357 Pre => True,
358 Post => True
359 is
360 FP, Encoded_P1, Encoded_P2 : Word32;
361 begin
362 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
363
364 -- FP register: N, M1, M2 encoded as (actual_value - 2)
365 FP :=
366 Shift_Left (Word32 (Clk.N - 2), FP_N_SHIFT) or
367 Shift_Left (Word32 (Clk.M1 - 2), FP_M1_SHIFT) or
368 Shift_Left (Word32 (Clk.M2 - 2), FP_M2_SHIFT);
369
370 Registers.Write (FP0 (PLL), FP);
371 Registers.Write (FP1 (PLL), FP);
372
373 -- P1 encoding: bitmask (1 << (P1-1)) shifted into position
374 Encoded_P1 := Shift_Left (1, Natural (Clk.P1) - 1);
375
376 if Clk.P2 = 5 or Clk.P2 = 7
377 then
378 Encoded_P2 := DPLL_P2_5_OR_7;
379 else
380 Encoded_P2 := DPLL_P2_10_OR_14;
381 end if;
382
383 -- i945 DPLL register: no HIGH_SPEED bit, no PULSE_PHASE bits
384 Registers.Write
385 (Register => DPLL (PLL),
386 Value => DPLL_Mode (Display) or
387 DPLL_VGA_MODE_DIS or
388 Encoded_P2 or
389 Shift_Left (Encoded_P1, DPLL_P1_DIVIDER_SHIFT));
390 end Program_DPLL;
391
392 procedure On
393 (PLL : in T;
394 Port_Cfg : in Port_Config;
395 Success : out Boolean)
396 is
397 Target_Clock : constant Frequency_Type := Port_Cfg.Mode.Dotclock;
398 Clk : Clock_Type;
399 begin
400 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
401
402 Success := PLL in DPLLs;
403 Clk := Invalid_Clock;
404
405 if Success then
406 if Target_Clock <= 400_000_000 then
407 Calculate_Clock_Parameters
408 (Display => Port_Cfg.Display,
409 Target_Dotclock => Target_Clock,
410 Reference_Clock => 96_000_000,
411 Best_Clock => Clk,
412 Valid => Success);
413 else
414 Success := False;
415 pragma Debug (Debug.Put ("WARNING: Targeted clock too high: "));
416 pragma Debug (Debug.Put_Int64 (Target_Clock));
417 pragma Debug (Debug.Put (" > "));
418 pragma Debug (Debug.Put_Int32 (400_000_000));
419 pragma Debug (Debug.New_Line);
420 pragma Debug (Debug.New_Line);
421 end if;
422 end if;
423
424 if Success then
425 Program_DPLL (PLL, Port_Cfg.Display, Clk);
426
427 Registers.Set_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
428 Registers.Posting_Read (DPLL (PLL));
429 Time.U_Delay (150);
430 end if;
431 end On;
432
433 procedure Off (PLL : T)
434 is
435 begin
436 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
437
438 if PLL in DPLLs then
439 Registers.Unset_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
440 end if;
441 end Off;
442
443 ----------------------------------------------------------------------------
444
445 procedure Initialize
446 is
447 begin
448 PLLs :=
449 (DPLLs =>
450 (Use_Count => 0,
451 Mode => Invalid_Mode));
452 end Initialize;
453
454 procedure Alloc_Configurable
455 (Port_Cfg : in Port_Config;
456 PLL : out T;
457 Success : out Boolean)
458 with
459 Pre => True
460 is
461 function Config_Matches (PE : PLL_State) return Boolean
462 is
463 begin
464 return PE.Mode = Port_Cfg.Mode;
465 end Config_Matches;
466 begin
467 -- try to find shareable PLL
468 for P in DPLLs loop
469 Success := PLLs (P).Use_Count /= 0 and
470 PLLs (P).Use_Count /= Count_Range'Last and
471 Config_Matches (PLLs (P));
472 if Success then
473 PLL := P;
474 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
475 return;
476 end if;
477 end loop;
478
479 -- try to find free PLL
480 for P in DPLLs loop
481 if PLLs (P).Use_Count = 0 then
482 PLL := P;
483 On (PLL, Port_Cfg, Success);
484 if Success then
485 PLLs (PLL) :=
486 (Use_Count => 1,
487 Mode => Port_Cfg.Mode);
488 end if;
489 return;
490 end if;
491 end loop;
492
493 PLL := Invalid;
494 end Alloc_Configurable;
495
496 procedure Alloc
497 (Port_Cfg : in Port_Config;
498 PLL : out T;
499 Success : out Boolean)
500 is
501 -- On i945, DPLL-to-pipe mapping is fixed:
502 -- LVDS -> Pipe B -> DPLL_B, all others -> Pipe A -> DPLL_A
503 Target : constant DPLLs :=
504 (if Port_Cfg.Display = LVDS then DPLL_B else DPLL_A);
505 begin
506 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
507
508 PLL := Target;
509
510 if PLLs (Target).Use_Count /= 0 and
511 PLLs (Target).Use_Count /= Count_Range'Last and
512 PLLs (Target).Mode = Port_Cfg.Mode
513 then
514 -- Share existing PLL with matching mode
515 PLLs (Target).Use_Count := PLLs (Target).Use_Count + 1;
516 Success := True;
517 elsif PLLs (Target).Use_Count = 0 then
518 -- Program the PLL
519 On (Target, Port_Cfg, Success);
520 if Success then
521 PLLs (Target) :=
522 (Use_Count => 1,
523 Mode => Port_Cfg.Mode);
524 end if;
525 else
526 PLL := Invalid;
527 Success := False;
528 end if;
529 end Alloc;
530
531 procedure Free (PLL : T)
532 is
533 begin
534 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
535
536 if PLL in DPLLs then
537 if PLLs (PLL).Use_Count /= 0 then
538 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1;
539 if PLLs (PLL).Use_Count = 0 then
540 Off (PLL);
541 end if;
542 end if;
543 end if;
544 end Free;
545
546 procedure All_Off
547 is
548 begin
549 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
550
551 for PLL in DPLLs loop
552 Off (PLL);
553 end loop;
554 end All_Off;
555
556 function Register_Value (PLL : T) return Word32
557 is
558 begin
559 return (if PLL = DPLL_B then 1 else 0);
560 end Register_Value;
561
562end HW.GFX.GMA.PLLs;