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review.sourcearcade.org / libgfxinit / 3652e9c5ace183f9cbaf6910d8aad6908a27231f / . / common / g45 / hw-gfx-gma-plls.adb
blob: 5db76d62d4783eb7ee9fba6f77c62e8977fd2ea2 [file] [log] [blame]
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with HW.Time;
16with HW.GFX.GMA.Config;
17with HW.GFX.GMA.Registers;
18
19with HW.Debug;
20with GNAT.Source_Info;
21
22package body HW.GFX.GMA.PLLs
23with
24 Refined_State => (State => PLLs)
25is
26
27 Debug_Clocks : constant Boolean := False;
28
29 type Count_Range is new Natural range 0 .. 2;
30
31 type PLL_State is record
32 Use_Count : Count_Range;
33 Used_For_DP : Boolean;
34 Link_Rate : DP_Bandwidth;
35 Mode : Mode_Type;
36 end record;
37
38 type PLL_State_Array is array (DPLLs) of PLL_State;
39
40 PLLs : PLL_State_Array;
41
42 ----------------------------------------------------------------------------
43
44 subtype N_Range is Int64 range 3 .. 8;
45 subtype M_Range is Int64 range 70 .. 138;
46 subtype M1_Range is Int64 range 10 .. 25;
47 subtype M2_Range is Int64 range 4 .. 13;
48 subtype P_Range is Int64 range 5 .. 112;
49 subtype P1_Range is Int64 range 1 .. 8;
50 subtype P2_Range is Int64 range 5 .. 14;
51 subtype VCO_Range is Int64 range 1400000000 .. 3500000000;
52 subtype Clock_Range is HW.GFX.Frequency_Type;
53
54 type Clock_Type is
55 record
56 N : N_Range;
57 M1 : M1_Range;
58 M2 : M2_Range;
59 P1 : P1_Range;
60 P2 : P2_Range;
61 M : M_Range;
62 P : P_Range;
63 VCO : VCO_Range;
64 Reference_Clock : Clock_Range;
65 Dotclock : Clock_Range;
66 end record;
67
68 Invalid_Clock : constant Clock_Type := Clock_Type'
69 (N => N_Range'Last,
70 M1 => M1_Range'Last,
71 M2 => M2_Range'Last,
72 P1 => P1_Range'Last,
73 P2 => P2_Range'Last,
74 Reference_Clock => Clock_Range'Last,
75 M => M_Range'Last,
76 P => P_Range'Last,
77 VCO => VCO_Range'Last,
78 Dotclock => Clock_Range'Last);
79
80 type Limits_Type is
81 record
82 N_Lower : N_Range;
83 N_Upper : N_Range;
84 M_Lower : M_Range;
85 M_Upper : M_Range;
86 M1_Lower : M1_Range;
87 M1_Upper : M1_Range;
88 M2_Lower : M2_Range;
89 M2_Upper : M2_Range;
90 P_Lower : P_Range;
91 P_Upper : P_Range;
92 P1_Lower : P1_Range;
93 P1_Upper : P1_Range;
94 P2_Fast : P2_Range;
95 P2_Slow : P2_Range;
96 P2_Threshold : Clock_Range;
97 VCO_Lower : VCO_Range;
98 VCO_Upper : VCO_Range;
99 end record;
100
101 LVDS_Single_Limits : constant Limits_Type := Limits_Type'
102 (N_Lower => 3, N_Upper => 5,
103 M_Lower => 104, M_Upper => 138,
104 M1_Lower => 19, M1_Upper => 25, -- this is capped by M_Upper >= 5 * M1 + M2_Lower
105 M2_Lower => 7, M2_Upper => 13,
106 P_Lower => 28, P_Upper => 112,
107 P1_Lower => 2, P1_Upper => 8,
108 P2_Fast => 14, P2_Slow => 14,
109 P2_Threshold => Clock_Range'First,
110 VCO_Lower => 1_750_000_000, VCO_Upper => 3_500_000_000);
111 LVDS_Dual_Limits : constant Limits_Type := Limits_Type'
112 (N_Lower => 3, N_Upper => 5,
113 M_Lower => 104, M_Upper => 138,
114 M1_Lower => 19, M1_Upper => 25,
115 M2_Lower => 7, M2_Upper => 13,
116 P_Lower => 14, P_Upper => 56,
117 P1_Lower => 2, P1_Upper => 6,
118 P2_Fast => 7, P2_Slow => 7,
119 P2_Threshold => Clock_Range'First,
120 VCO_Lower => 1_750_000_000, VCO_Upper => 3_500_000_000);
121 SDVO_Limits : constant Limits_Type := Limits_Type'
122 (N_Lower => 3, N_Upper => 6,
123 M_Lower => 104, M_Upper => 138,
124 M1_Lower => 16, M1_Upper => 25,
125 M2_Lower => 7, M2_Upper => 13,
126 P_Lower => 10, P_Upper => 30,
127 P1_Lower => 1, P1_Upper => 3,
128 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
129 P2_Fast => 5, P2_Slow => 10,
130 P2_Threshold => 270_000_000,
131 VCO_Lower => 1_750_000_000, VCO_Upper => 3_500_000_000);
132 HDMI_Analog_Limits : constant Limits_Type := Limits_Type'
133 (N_Lower => 3, N_Upper => 6,
134 M_Lower => 104, M_Upper => 138,
135 M1_Lower => 18, M1_Upper => 25,
136 M2_Lower => 7, M2_Upper => 13,
137 P_Lower => 5, P_Upper => 80,
138 P1_Lower => 1, P1_Upper => 8,
139 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
140 P2_Fast => 5, P2_Slow => 10,
141 P2_Threshold => 165_000_000,
142 VCO_Lower => 1_750_000_000, VCO_Upper => 3_500_000_000);
143 All_Other_Limits : constant Limits_Type := Limits_Type'
144 (N_Lower => 3, N_Upper => 8,
145 M_Lower => 70, M_Upper => 120,
146 M1_Lower => 10, M1_Upper => 20,
147 M2_Lower => 5, M2_Upper => 9,
148 P_Lower => 5, P_Upper => 80,
149 P1_Lower => 1, P1_Upper => 8,
150 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
151 P2_Fast => 5, P2_Slow => 10,
152 P2_Threshold => 200_000_000,
153 VCO_Lower => 1_400_000_000, VCO_Upper => 2_800_000_000);
154
155 ----------------------------------------------------------------------------
156
157 type Regs is array (DPLLs) of Registers.Registers_Index;
158
159 DPLL : constant Regs := Regs'(Registers.GMCH_DPLL_A, Registers.GMCH_DPLL_B);
160 DPLL_VCO_ENABLE : constant := 1 * 2 ** 31;
161 DPLL_VGA_MODE_DIS : constant := 1 * 2 ** 28;
162 DPLL_P2_10_OR_14 : constant := 0 * 2 ** 24;
163 DPLL_P2_5_OR_7 : constant := 1 * 2 ** 24;
164 DPLL_P1_DIVIDER_SHIFT : constant := 16;
165 DPLL_SDVOCLK : constant := 2 * 2 ** 13;
166 DPLL_PULSE_PHASE_MASK : constant := 15 * 2 ** 9;
167 DPLL_PULSE_PHASE_6 : constant := 6 * 2 ** 9;
168
169 DPLL_HIGH_SPEED : constant := 1 * 2 ** 30;
170 DPLL_MODE_LVDS : constant := 2 * 2 ** 26;
171 DPLL_MODE_DAC : constant := 1 * 2 ** 26;
172 DPLL_DREFCLK : constant := 0 * 2 ** 13;
173 DPLL_SSC : constant := 3 * 2 ** 13;
174
175 MODE_DPLL_DAC : constant Word32 := Word32'
176 (DPLL_MODE_DAC or DPLL_DREFCLK);
177
178 MODE_DPLL_HDMI : constant Word32 := Word32'
179 (DPLL_MODE_DAC or DPLL_DREFCLK or DPLL_HIGH_SPEED);
180
181 MODE_DPLL_LVDS : constant Word32 := Word32'
182 (DPLL_MODE_LVDS or DPLL_SSC);
183
184 MODE_DPLL_DP : constant Word32 := Word32'
185 (DPLL_MODE_DAC or DPLL_SSC or DPLL_HIGH_SPEED);
186
187 type DPLL_Mode_Array is array (Display_Type) of Word32;
188
189 DPLL_Mode : constant DPLL_Mode_Array := DPLL_Mode_Array'
190 (LVDS => MODE_DPLL_LVDS,
191 DP => MODE_DPLL_DP,
192 HDMI => MODE_DPLL_HDMI,
193 VGA => MODE_DPLL_DAC,
194 Others => MODE_DPLL_HDMI); --TODO Add SDVO
195
196 FP0 : constant Regs := Regs'(Registers.GMCH_FPA0, Registers.GMCH_FPB0);
197 FP1 : constant Regs := Regs'(Registers.GMCH_FPA1, Registers.GMCH_FPB1);
198 FP_DOUBLE_CLOCK : constant := 1 * 2 ** 27;
199 FP_N_SHIFT : constant := 16;
200 FP_M1_SHIFT : constant := 8;
201 FP_M2_SHIFT : constant := 0;
202
203 ----------------------------------------------------------------------------
204
205 procedure Verify_Parameters
206 (N : in N_Range;
207 M1 : in M1_Range;
208 M2 : in M2_Range;
209 P1 : in P1_Range;
210 P2 : in P2_Range;
211 Reference_Clock : in Clock_Range;
212 Current_Limits : in Limits_Type;
213 Result : out Clock_Type;
214 Valid : out Boolean)
215 with
216 Global => null,
217 Pre => True,
218 Post => True
219 is
220 M : Int64;
221 P : Int64;
222 VCO : Int64;
223 Dotclock : Int64;
224 begin
225 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
226
227 M := 5 * M1 + M2;
228 P := P1 * P2;
229 VCO := (Int64 (Reference_Clock) * M) / N;
230 Dotclock := VCO / P;
231
232 pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range."));
233 pragma Debug (Debug_Clocks and (Current_Limits.P2_Fast /= P2 and P2 /= Current_Limits.P2_Slow ), Debug.Put_Line ("P2 out of range."));
234 pragma Debug (Debug_Clocks and not (Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper ), Debug.Put_Line ("P out of range."));
235 pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range."));
236 pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range."));
237 -- pragma Debug (Debug_Clocks and not (M2 <= M1 ), Debug.Put_Line ("M1 greater thant M2."));
238 pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper ), Debug.Put_Line ("N out of range."));
239 pragma Debug (Debug_Clocks and not (Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper ), Debug.Put_Line ("M out of range."));
240 pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range."));
241
242 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Line ("Dotclock too low."));
243 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Int64 (Dotclock));
244 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.New_Line);
245
246 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Line ("Dotclock too high."));
247 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Int64 (Dotclock));
248 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.New_Line);
249
250 Valid :=
251 Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper and
252 (Current_Limits.P2_Fast = P2 or P2 = Current_Limits.P2_Slow) and
253 Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper and
254 Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper and
255 Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper and
256 Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper and
257 Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper and
258 Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and
259 Int64 (Clock_Range'First) <= Dotclock and
260 Dotclock <= Int64 (Clock_Range'Last);
261
262 if Valid
263 then
264 Result := Clock_Type'
265 (N => N,
266 M1 => M1,
267 M2 => M2,
268 P1 => P1,
269 P2 => P2,
270 Reference_Clock => Reference_Clock,
271 M => M,
272 P => P,
273 VCO => VCO,
274 Dotclock => Clock_Range (Dotclock));
275 else
276 Result := Invalid_Clock;
277 end if;
278
279 end Verify_Parameters;
280
281 procedure Calculate_Clock_Parameters
282 (Display : in Display_Type;
283 Target_Dotclock : in Clock_Range;
284 Reference_Clock : in Clock_Range;
285 Best_Clock : out Clock_Type;
286 Valid : out Boolean)
287 with
288 Global => null,
289 Pre => True,
290 Post => True
291 is
292 Limits : constant Limits_Type :=
293 (case Display is
294 when LVDS =>
295 (if Target_Dotclock >= Config.LVDS_Dual_Threshold then
296 LVDS_Dual_Limits
297 else
298 LVDS_Single_Limits),
299 when HDMI => HDMI_Analog_Limits,
300 when VGA => HDMI_Analog_Limits,
301 when others => All_Other_Limits); --TODO add SDVO type, needs other limits
302
303 P2 : P2_Range;
304 Best_Delta : Int64 := Int64'Last;
305 Current_Delta : Int64;
306 Current_Clock : Clock_Type;
307 Registers_Valid : Boolean;
308 begin
309 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
310
311 Valid := False;
312 Best_Clock := Invalid_Clock;
313
314 if Target_Dotclock <= Limits.P2_Threshold then
315 P2 := Limits.P2_Slow;
316 else
317 P2 := Limits.P2_Fast;
318 end if;
319
320 for N in N_Range range Limits.N_Lower .. Limits.N_Upper
321 loop
322 -- reverse loops as hardware prefers higher values
323 for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
324 loop
Nico Huber3652e9c2022-09-04 14:29:30 +0000[diff] [blame^]325 pragma Loop_Invariant (True);
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]326 for M2 in reverse M2_Range range Limits.M2_Lower .. Int64'Min (Limits.M2_Upper, M1)
327 loop
Nico Huber3652e9c2022-09-04 14:29:30 +0000[diff] [blame^]328 pragma Loop_Invariant (True);
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]329 for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
330 loop
331 Verify_Parameters
332 (N => N,
333 M1 => M1,
334 M2 => M2,
335 P1 => P1,
336 P2 => P2,
337 Reference_Clock => Reference_Clock,
338 Current_Limits => Limits,
339 Result => Current_Clock,
340 Valid => Registers_Valid);
341
342 if Registers_Valid
343 then
344 if Current_Clock.Dotclock > Target_Dotclock
345 then
346 Current_Delta := Current_Clock.Dotclock - Target_Dotclock;
347 else
348 Current_Delta := Target_Dotclock - Current_Clock.Dotclock;
349 end if;
350
351 if Current_Delta < Best_Delta
352 then
353 Best_Delta := Current_Delta;
354 Best_Clock := Current_Clock;
355 Valid := True;
356 end if;
357
358 pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: "));
359 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock));
360 pragma Debug (Debug_Clocks, Debug.Put ("/"));
361 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock));
362 pragma Debug (Debug_Clocks, Debug.Put ("/"));
363 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta));
364 pragma Debug (Debug_Clocks, Debug.Put_Line ("."));
365
366 end if;
367 end loop;
368 end loop;
369 end loop;
370 end loop;
371
372 pragma Debug (Valid, Debug.Put_Line ("Valid clock found."));
373 pragma Debug (Valid, Debug.Put ("Best/Target/Delta: "));
374 pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock));
375 pragma Debug (Valid, Debug.Put ("/"));
376 pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock));
377 pragma Debug (Valid, Debug.Put ("/"));
378 pragma Debug (Valid, Debug.Put_Int64 (Best_Delta));
379 pragma Debug (Valid, Debug.Put_Line ("."));
380 pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
381
382 end Calculate_Clock_Parameters;
383
384 procedure Program_DPLL
385 (PLL : DPLLs;
386 Display : Display_Type;
387 Clk : Clock_Type)
388 with
389 Global => (In_Out => Registers.Register_State),
390 Pre => True,
391 Post => True
392 is
393 FP, Encoded_P1, Encoded_P2 : Word32;
394 begin
395 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
396
397 FP :=
398 Shift_Left (Word32 (Clk.N - 2), FP_N_SHIFT) or
399 Shift_Left (Word32 (Clk.M1 - 2), FP_M1_SHIFT) or
400 Shift_Left (Word32 (Clk.M2 - 2), FP_M2_SHIFT);
401
402 Registers.Write (FP0 (PLL), FP);
403 Registers.Write (FP1 (PLL), FP);
404
405 Encoded_P1 := Shift_Left (1, Natural (Clk.P1) - 1);
406
407 if Clk.P2 = 5 or Clk.P2 = 7
408 then
409 Encoded_P2 := DPLL_P2_5_OR_7;
410 else
411 Encoded_P2 := DPLL_P2_10_OR_14;
412 end if;
413
414 Registers.Write
415 (Register => DPLL (PLL),
416 Value => DPLL_Mode (Display) or
417 DPLL_VGA_MODE_DIS or
418 DPLL_PULSE_PHASE_6 or
419 Encoded_P2 or
420 Shift_Left (Encoded_P1, DPLL_P1_DIVIDER_SHIFT));
421 end Program_DPLL;
422
423 procedure On
424 (PLL : in T;
425 Port_Cfg : in Port_Config;
426 Success : out Boolean)
427 is
428 Target_Clock : constant Frequency_Type :=
429 (if Port_Cfg.Display = DP then
430 DP_Symbol_Rate (Port_Cfg.DP.Bandwidth)
431 else
432 Port_Cfg.Mode.Dotclock);
433 Clk : Clock_Type;
434 begin
435 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
436
437 Success := PLL in DPLLs;
438 Clk := Invalid_Clock;
439
440 if Success then
441 if Port_Cfg.Display = DP then
442 Success := True;
443 -- we use static values for DP
444 case Port_Cfg.DP.Bandwidth is
445 when DP_Bandwidth_1_62 =>
446 Clk.N := 4;
447 Clk.M1 := 25;
448 Clk.M2 := 10;
449 Clk.P1 := 2;
450 Clk.P2 := 10;
451 when DP_Bandwidth_2_7 =>
452 Clk.N := 3;
453 Clk.M1 := 16;
454 Clk.M2 := 4;
455 Clk.P1 := 1;
456 Clk.P2 := 10;
457 when others =>
458 Success := False;
459 end case;
460 elsif Target_Clock <= 340_000_000 then
461 Calculate_Clock_Parameters
462 (Display => Port_Cfg.Display,
463 Target_Dotclock => Target_Clock,
464 -- should be, but doesn't has to be always the same:
465 Reference_Clock => 96_000_000,
466 Best_Clock => Clk,
467 Valid => Success);
468 else
469 Success := False;
470 pragma Debug (Debug.Put ("WARNING: Targeted clock too high: "));
471 pragma Debug (Debug.Put_Int64 (Target_Clock));
472 pragma Debug (Debug.Put (" > "));
473 pragma Debug (Debug.Put_Int32 (340_000_000));
474 pragma Debug (Debug.New_Line);
475 pragma Debug (Debug.New_Line);
476 end if;
477 end if;
478
479 if Success then
480 Program_DPLL (PLL, Port_Cfg.Display, Clk);
481
482 Registers.Set_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
483 Registers.Posting_Read (DPLL (PLL));
484 Time.U_Delay (150);
485 end if;
486 end On;
487
488 procedure Off (PLL : T)
489 is
490 begin
491 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
492
493 if PLL in DPLLs then
494 Registers.Unset_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
495 end if;
496 end Off;
497
498 ----------------------------------------------------------------------------
499
500 procedure Initialize
501 is
502 begin
503 PLLs :=
504 (DPLLs =>
505 (Use_Count => 0,
506 Used_For_DP => False,
507 Link_Rate => DP_Bandwidth'First,
508 Mode => Invalid_Mode));
509 end Initialize;
510
511 procedure Alloc_Configurable
512 (Port_Cfg : in Port_Config;
513 PLL : out T;
514 Success : out Boolean)
515 with
516 Pre => True
517 is
518 function Config_Matches (PE : PLL_State) return Boolean
519 is
520 begin
521 return
522 PE.Used_For_DP = (Port_Cfg.Display = DP) and
523 ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or
524 (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode));
525 end Config_Matches;
526 begin
527 -- try to find shareable PLL
528 for P in DPLLs loop
529 Success := PLLs (P).Use_Count /= 0 and
530 PLLs (P).Use_Count /= Count_Range'Last and
531 Config_Matches (PLLs (P));
532 if Success then
533 PLL := P;
534 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
535 return;
536 end if;
537 end loop;
538
539 -- try to find free PLL
540 for P in DPLLs loop
541 if PLLs (P).Use_Count = 0 then
542 PLL := P;
543 On (PLL, Port_Cfg, Success);
544 if Success then
545 PLLs (PLL) :=
546 (Use_Count => 1,
547 Used_For_DP => Port_Cfg.Display = DP,
548 Link_Rate => Port_Cfg.DP.Bandwidth,
549 Mode => Port_Cfg.Mode);
550 end if;
551 return;
552 end if;
553 end loop;
554
555 PLL := Invalid;
556 end Alloc_Configurable;
557
558 procedure Alloc
559 (Port_Cfg : in Port_Config;
560 PLL : out T;
561 Success : out Boolean)
562 is
563 begin
564 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
565
566 if Port_Cfg.Port = DIGI_A then
567 PLL := Invalid;
568 Success := True;
569 else
570 Alloc_Configurable (Port_Cfg, PLL, Success);
571 end if;
572 end Alloc;
573
574 procedure Free (PLL : T)
575 is
576 begin
577 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
578
579 if PLL in DPLLs then
580 if PLLs (PLL).Use_Count /= 0 then
581 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1;
582 if PLLs (PLL).Use_Count = 0 then
583 Off (PLL);
584 end if;
585 end if;
586 end if;
587 end Free;
588
589 procedure All_Off
590 is
591 begin
592 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
593
594 for PLL in DPLLs loop
595 Off (PLL);
596 end loop;
597 end All_Off;
598
599 function Register_Value (PLL : T) return Word32
600 is
601 begin
602 return (if PLL = DPLL_B then 1 else 0);
603 end Register_Value;
604
605end HW.GFX.GMA.PLLs;