| -- |
| -- Copyright (C) 2015-2016 secunet Security Networks AG |
| -- |
| -- This program is free software; you can redistribute it and/or modify |
| -- it under the terms of the GNU General Public License as published by |
| -- the Free Software Foundation; either version 2 of the License, or |
| -- (at your option) any later version. |
| -- |
| -- This program is distributed in the hope that it will be useful, |
| -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
| -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| -- GNU General Public License for more details. |
| -- |
| |
| private package HW.GFX.GMA.Config |
| with |
| Initializes => Valid_Port_GPU |
| is |
| |
| CPU : constant CPU_Type := <<CPU>>; |
| |
| CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>; |
| |
| Internal_Display : constant Internal_Type := <<INTERNAL_PORT>>; |
| |
| Analog_I2C_Port : constant PCH_Port := <<ANALOG_I2C_PORT>>; |
| |
| EDP_Low_Voltage_Swing : constant Boolean := False; |
| |
| Default_MMIO_Base : constant := <<DEFAULT_MMIO_BASE>>; |
| |
| LVDS_Dual_Threshold : constant := 95_000_000; |
| |
| ---------------------------------------------------------------------------- |
| |
| Has_Internal_Display : constant Boolean := Internal_Display /= None; |
| Internal_Is_EDP : constant Boolean := Internal_Display = DP; |
| |
| ----- CPU pipe: -------- |
| Disable_Trickle_Feed : constant Boolean := not |
| (CPU in Haswell .. Broadwell); |
| Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell; |
| Has_EDP_Transcoder : constant Boolean := CPU >= Haswell; |
| Has_Pipe_DDI_Func : constant Boolean := CPU >= Haswell; |
| Has_Trans_Clk_Sel : constant Boolean := CPU >= Haswell; |
| Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; |
| Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; |
| Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; |
| Has_Plane_Control : constant Boolean := CPU >= Broxton; |
| Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; |
| Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; |
| VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge; |
| |
| ----- Panel power: ----- |
| Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge; |
| Has_PP_Port_Select : constant Boolean := CPU <= Ivybridge; |
| Use_PP_VDD_Override : constant Boolean := CPU <= Ivybridge; |
| |
| ----- PCH/FDI: --------- |
| Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or |
| (CPU in Broadwell .. Haswell |
| and CPU_Var = Normal); |
| |
| Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell; |
| |
| VGA_Has_Sync_Disable : constant Boolean := CPU <= Ivybridge; |
| |
| Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge; |
| |
| Has_DPLL_SEL : constant Boolean := CPU in Ironlake .. Ivybridge; |
| Has_FDI_BPC : constant Boolean := CPU in Ironlake .. Ivybridge; |
| Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge; |
| Has_Trans_DP_Ctl : constant Boolean := CPU in |
| Sandybridge .. Ivybridge; |
| Has_FDI_C : constant Boolean := CPU = Ivybridge; |
| |
| Has_FDI_RX_Power_Down : constant Boolean := CPU in Haswell .. Broadwell; |
| |
| ----- DDI: ------------- |
| End_EDP_Training_Late : constant Boolean := CPU in Haswell .. Broadwell; |
| Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell; |
| Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell; |
| Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell |
| and CPU_Var = ULT) or |
| CPU >= Skylake; |
| |
| Has_DDI_D : constant Boolean := (CPU in Haswell .. Broadwell |
| and CPU_Var = Normal) |
| or CPU >= Skylake; |
| |
| Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; |
| |
| Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC) |
| |
| Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; |
| |
| ----- Power: ----------- |
| Has_IPS : constant Boolean := (CPU = Haswell and |
| CPU_Var = ULT) or |
| CPU = Broadwell; |
| Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell; |
| |
| Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell; |
| |
| ----- GTT: ------------- |
| Fold_39Bit_GTT_PTE : constant Boolean := CPU <= Haswell; |
| |
| ---------------------------------------------------------------------------- |
| |
| Max_Pipe : constant Pipe_Index := |
| (if CPU <= Sandybridge |
| then Secondary |
| else Tertiary); |
| |
| type Supported_Pipe_Array is array (Pipe_Index) of Boolean; |
| Supported_Pipe : constant Supported_Pipe_Array := |
| (Primary => Primary <= Max_Pipe, |
| Secondary => Secondary <= Max_Pipe, |
| Tertiary => Tertiary <= Max_Pipe); |
| |
| type Valid_Per_Port is array (Port_Type) of Boolean; |
| type Valid_Per_GPU is array (CPU_Type) of Valid_Per_Port; |
| Valid_Port_GPU : Valid_Per_GPU := |
| (Ironlake => |
| (Disabled => False, |
| Internal => Config.Internal_Display = LVDS, |
| others => True), |
| Sandybridge => |
| (Disabled => False, |
| Internal => Config.Internal_Display = LVDS, |
| others => True), |
| Ivybridge => |
| (Disabled => False, |
| Internal => Config.Internal_Display /= None, |
| others => True), |
| Haswell => |
| (Disabled => False, |
| Internal => Config.Internal_Display = DP, |
| HDMI3 => CPU_Var = Normal, |
| DP3 => CPU_Var = Normal, |
| Analog => CPU_Var = Normal, |
| others => True), |
| Broadwell => |
| (Disabled => False, |
| Internal => Config.Internal_Display = DP, |
| HDMI3 => CPU_Var = Normal, |
| DP3 => CPU_Var = Normal, |
| Analog => CPU_Var = Normal, |
| others => True), |
| Broxton => |
| (Internal => Config.Internal_Display = DP, |
| DP1 => True, |
| DP2 => True, |
| HDMI1 => True, |
| HDMI2 => True, |
| others => False), |
| Skylake => |
| (Disabled => False, |
| Internal => Config.Internal_Display = DP, |
| Analog => False, |
| others => True)) |
| with |
| Part_Of => GMA.Config_State; |
| Valid_Port : Valid_Per_Port renames Valid_Port_GPU (CPU); |
| |
| Last_Digital_Port : constant Digital_Port := |
| (if Has_DDI_D then DIGI_D else DIGI_C); |
| |
| ---------------------------------------------------------------------------- |
| |
| type FDI_Per_Port is array (Port_Type) of Boolean; |
| Is_FDI_Port : constant FDI_Per_Port := |
| (case CPU is |
| when Ironlake .. Ivybridge => FDI_Per_Port' |
| (Internal => Internal_Display = LVDS, |
| others => True), |
| when Haswell => FDI_Per_Port' |
| (Analog => True, |
| others => False), |
| when Broadwell => FDI_Per_Port' |
| (Analog => CPU_Var = Normal, |
| others => False), |
| when others => FDI_Per_Port' |
| (others => False)); |
| |
| type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count; |
| FDI_Lane_Count : constant FDI_Lanes_Per_Port := |
| (DIGI_D => DP_Lane_Count_2, |
| others => |
| (if CPU in Ironlake .. Ivybridge then |
| DP_Lane_Count_4 |
| else |
| DP_Lane_Count_2)); |
| |
| FDI_Training : constant FDI_Training_Type := |
| (case CPU is |
| when Ironlake => Simple_Training, |
| when Sandybridge => Full_Training, |
| when others => Auto_Training); |
| |
| ---------------------------------------------------------------------------- |
| |
| Default_CDClk_Freq : constant Frequency_Type := |
| (case CPU is |
| when Ironlake | |
| Haswell | |
| Broadwell => 450_000_000, |
| when Sandybridge | |
| Ivybridge => 400_000_000, |
| when Broxton => 288_000_000, |
| when Skylake => 337_500_000); |
| |
| Default_RawClk_Freq : constant Frequency_Type := |
| (case CPU is |
| when Ironlake | |
| Sandybridge | |
| Ivybridge => 125_000_000, |
| when Haswell | |
| Broadwell => (if CPU_Var = Normal then |
| 125_000_000 |
| else |
| 24_000_000), |
| when Broxton => Frequency_Type'First, -- none needed |
| when Skylake => 24_000_000); |
| |
| ---------------------------------------------------------------------------- |
| |
| -- Maximum source width with enabled scaler. This only accounts |
| -- for simple 1:1 pipe:scaler mappings. |
| |
| type Width_Per_Pipe is array (Pipe_Index) of Width_Type; |
| |
| Maximum_Scalable_Width : constant Width_Per_Pipe := |
| (case CPU is |
| when Ironlake..Haswell => |
| (Primary => 4096, |
| Secondary => 2048, |
| Tertiary => 2048), |
| when Broadwell..Skylake => |
| (Primary => 4096, |
| Secondary => 4096, |
| Tertiary => 4096)); |
| |
| ---------------------------------------------------------------------------- |
| |
| -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D |
| HDMI_Max_Clock_24bpp : constant Frequency_Type := |
| (if CPU >= Haswell then 300_000_000 else 225_000_000); |
| |
| end HW.GFX.GMA.Config; |