gma broxton: Implement pre-PLL setup for DDI PHYs
Some lane configuration that's supposed to happen before enabling
the display PLL.
Change-Id: I08ec3ac26164061b19d695ab600d6bb9eeadd7ad
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18424
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/broxton/hw-gfx-gma-ddi_phy.adb b/common/broxton/hw-gfx-gma-ddi_phy.adb
index 83c7c28..b1e8344 100644
--- a/common/broxton/hw-gfx-gma-ddi_phy.adb
+++ b/common/broxton/hw-gfx-gma-ddi_phy.adb
@@ -259,4 +259,67 @@
Unset_Mask (BXT_P_CR_GT_DISP_PWRON, GT_DISPLAY_POWER_ON (Phy));
end Power_Off;
+ ----------------------------------------------------------------------------
+
+ type Lanes is range 0 .. 3;
+ type Lane_Reg_Array is array (Lanes) of Registers_Index;
+
+ type Port_TX_Regs is record
+ DW14_LN : Lane_Reg_Array;
+ end record;
+ type Port_TX_Array is array (DDI_Phy_Port) of Port_TX_Regs;
+
+ PORT_TX : constant Port_TX_Array :=
+ (DIGI_A =>
+ (DW14_LN =>
+ (BXT_PORT_TX_DW14_LN0_A,
+ BXT_PORT_TX_DW14_LN1_A,
+ BXT_PORT_TX_DW14_LN2_A,
+ BXT_PORT_TX_DW14_LN3_A)),
+ DIGI_B =>
+ (DW14_LN =>
+ (BXT_PORT_TX_DW14_LN0_B,
+ BXT_PORT_TX_DW14_LN1_B,
+ BXT_PORT_TX_DW14_LN2_B,
+ BXT_PORT_TX_DW14_LN3_B)),
+ DIGI_C =>
+ (DW14_LN =>
+ (BXT_PORT_TX_DW14_LN0_C,
+ BXT_PORT_TX_DW14_LN1_C,
+ BXT_PORT_TX_DW14_LN2_C,
+ BXT_PORT_TX_DW14_LN3_C)));
+
+ PORT_TX_DW14_LN_LATENCY_OPTIM : constant := 1 * 2 ** 30;
+
+ procedure Pre_PLL (Port_Cfg : Port_Config)
+ is
+ type Lane_Values is array (Lanes) of Word32;
+ Lane_Optim : constant Lane_Values :=
+ (if Port_Cfg.Display = HDMI or
+ Port_Cfg.DP.Lane_Count = DP_Lane_Count_4
+ then
+ (0 => PORT_TX_DW14_LN_LATENCY_OPTIM,
+ 1 => 0,
+ 2 => PORT_TX_DW14_LN_LATENCY_OPTIM,
+ 3 => PORT_TX_DW14_LN_LATENCY_OPTIM)
+ elsif Port_Cfg.DP.Lane_Count = DP_Lane_Count_2 then
+ (0 => PORT_TX_DW14_LN_LATENCY_OPTIM,
+ 1 => 0,
+ 2 => PORT_TX_DW14_LN_LATENCY_OPTIM,
+ 3 => 0)
+ else
+ (Lanes => 0));
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ if Port_Cfg.Port in DDI_Phy_Port then
+ for Lane in Lanes loop
+ Unset_And_Set_Mask
+ (Register => PORT_TX (Port_Cfg.Port).DW14_LN (Lane),
+ Mask_Unset => PORT_TX_DW14_LN_LATENCY_OPTIM,
+ Mask_Set => Lane_Optim (Lane));
+ end loop;
+ end if;
+ end Pre_PLL;
+
end HW.GFX.GMA.DDI_Phy;
diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads
index 51221b0..a303b2f 100644
--- a/common/broxton/hw-gfx-gma-ddi_phy.ads
+++ b/common/broxton/hw-gfx-gma-ddi_phy.ads
@@ -21,4 +21,6 @@
subtype DDI_Phy_Port is GPU_Port range DIGI_A .. DIGI_C;
+ procedure Pre_PLL (Port_Cfg : Port_Config);
+
end HW.GFX.GMA.DDI_Phy;
diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb
index 8c87507..7da47f2 100644
--- a/common/broxton/hw-gfx-gma-plls.adb
+++ b/common/broxton/hw-gfx-gma-plls.adb
@@ -17,6 +17,7 @@
with HW.GFX.GMA.Config;
with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.DDI_Phy;
use HW.GFX.GMA.Registers;
@@ -461,6 +462,7 @@
end if;
if Success then
+ DDI_Phy.Pre_PLL (Port_Cfg);
Program_DPLL (PLL, Clock);
end if;
end Alloc;
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 84caefc..4e58651 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -284,7 +284,15 @@
BXT_PORT_PLL_9_C,
BXT_PORT_PLL_10_C,
BXT_PORT_PCS_DW12_01_B,
+ BXT_PORT_TX_DW14_LN0_B,
+ BXT_PORT_TX_DW14_LN1_B,
+ BXT_PORT_TX_DW14_LN2_B,
+ BXT_PORT_TX_DW14_LN3_B,
BXT_PORT_PCS_DW12_01_C,
+ BXT_PORT_TX_DW14_LN0_C,
+ BXT_PORT_TX_DW14_LN1_C,
+ BXT_PORT_TX_DW14_LN2_C,
+ BXT_PORT_TX_DW14_LN3_C,
BXT_PORT_PCS_DW12_GRP_B,
BXT_PORT_PCS_DW12_GRP_C,
BXT_DE_PLL_CTL,
@@ -521,6 +529,10 @@
BXT_PORT_REF_DW6_A,
BXT_PORT_REF_DW8_A,
BXT_PORT_PCS_DW12_01_A,
+ BXT_PORT_TX_DW14_LN0_A,
+ BXT_PORT_TX_DW14_LN1_A,
+ BXT_PORT_TX_DW14_LN2_A,
+ BXT_PORT_TX_DW14_LN3_A,
BXT_PORT_PCS_DW12_GRP_A);
pragma Warnings
@@ -960,6 +972,20 @@
BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
+ -- Broxton DDI PHY TX lane registers
+ BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
+ BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
+ BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
+ BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
+ BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
+ BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
+ BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
+ BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
+ BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
+ BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
+ BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
+ BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
+
-- Broxton DDI PHY ref registers
BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,