| commit | afadcace9e96289e3aff808c4fac5830c11bdc6c | [log] [tgz] |
|---|---|---|
| author | Nico Huber <nico.huber@secunet.com> | Wed Feb 08 13:41:38 2017 +0100 |
| committer | Nico Huber <nico.h@gmx.de> | Sat Jun 03 15:23:51 2017 +0200 |
| tree | 9cb10bccb194c7504a14c6f7e6f7fd7d97d3e0e6 | |
| parent | 4b0239f549c99b1c393f099fe21c7055860fbe7a [diff] [blame] |
gma broxton: Implement pre-PLL setup for DDI PHYs Some lane configuration that's supposed to happen before enabling the display PLL. Change-Id: I08ec3ac26164061b19d695ab600d6bb9eeadd7ad Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18424 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index 51221b0..a303b2f 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads
@@ -21,4 +21,6 @@ subtype DDI_Phy_Port is GPU_Port range DIGI_A .. DIGI_C; + procedure Pre_PLL (Port_Cfg : Port_Config); + end HW.GFX.GMA.DDI_Phy;