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Uwe Hermann515ab3d2009-05-15 17:02:34 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +00005 * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger
Uwe Hermann515ab3d2009-05-15 17:02:34 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <stdlib.h>
23#include <string.h>
Uwe Hermann515ab3d2009-05-15 17:02:34 +000024#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000026#include "hwaccess.h"
Uwe Hermann515ab3d2009-05-15 17:02:34 +000027
28uint32_t io_base_addr;
29struct pci_access *pacc;
Uwe Hermann8403ccb2009-05-16 21:39:19 +000030struct pci_dev *pcidev_dev = NULL;
Uwe Hermann515ab3d2009-05-15 17:02:34 +000031
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000032enum pci_bartype {
33 TYPE_MEMBAR,
34 TYPE_IOBAR,
35 TYPE_ROMBAR,
36 TYPE_UNKNOWN
37};
38
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000039uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
Uwe Hermann515ab3d2009-05-15 17:02:34 +000040{
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000041 uint64_t addr;
42 uint32_t upperaddr;
43 uint8_t headertype;
44 uint16_t supported_cycles;
45 enum pci_bartype bartype = TYPE_UNKNOWN;
Uwe Hermann515ab3d2009-05-15 17:02:34 +000046
Uwe Hermann515ab3d2009-05-15 17:02:34 +000047
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000048 headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
49 msg_pspew("PCI header type 0x%02x\n", headertype);
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000050
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000051 /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */
52 addr = pci_read_long(dev, bar);
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000053
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000054 /* Sanity checks. */
55 switch (headertype) {
56 case PCI_HEADER_TYPE_NORMAL:
57 switch (bar) {
58 case PCI_BASE_ADDRESS_0:
59 case PCI_BASE_ADDRESS_1:
60 case PCI_BASE_ADDRESS_2:
61 case PCI_BASE_ADDRESS_3:
62 case PCI_BASE_ADDRESS_4:
63 case PCI_BASE_ADDRESS_5:
64 if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
65 bartype = TYPE_IOBAR;
66 else
67 bartype = TYPE_MEMBAR;
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000068 break;
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000069 case PCI_ROM_ADDRESS:
70 bartype = TYPE_ROMBAR;
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000071 break;
72 }
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000073 break;
74 case PCI_HEADER_TYPE_BRIDGE:
75 switch (bar) {
76 case PCI_BASE_ADDRESS_0:
77 case PCI_BASE_ADDRESS_1:
78 if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
79 bartype = TYPE_IOBAR;
80 else
81 bartype = TYPE_MEMBAR;
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000082 break;
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000083 case PCI_ROM_ADDRESS1:
84 bartype = TYPE_ROMBAR;
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +000085 break;
Carl-Daniel Hailfinger295b3af2010-03-17 00:47:56 +000086 }
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000087 break;
88 case PCI_HEADER_TYPE_CARDBUS:
89 break;
90 default:
91 msg_perr("Unknown PCI header type 0x%02x, BAR type cannot be determined reliably.\n",
92 headertype);
93 break;
Uwe Hermann515ab3d2009-05-15 17:02:34 +000094 }
95
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000096 supported_cycles = pci_read_word(dev, PCI_COMMAND);
97
98 msg_pdbg("Requested BAR is ");
99 switch (bartype) {
100 case TYPE_MEMBAR:
101 msg_pdbg("MEM");
102 if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
103 msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
104 /* TODO: Abort here? */
105 }
106 msg_pdbg(", %sbit, %sprefetchable\n",
107 ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"),
108 (addr & 0x8) ? "" : "not ");
109 if ((addr & 0x6) == 0x4) {
110 /* The spec says that a 64-bit register consumes
111 * two subsequent dword locations.
112 */
113 upperaddr = pci_read_long(dev, bar + 4);
114 if (upperaddr != 0x00000000) {
115 /* Fun! A real 64-bit resource. */
116 if (sizeof(uintptr_t) != sizeof(uint64_t)) {
117 msg_perr("BAR unreachable!");
118 /* TODO: Really abort here? If multiple PCI devices match,
119 * we might never tell the user about the other devices.
120 */
121 return 0;
122 }
123 addr |= (uint64_t)upperaddr << 32;
124 }
125 }
126 addr &= PCI_BASE_ADDRESS_MEM_MASK;
127 break;
128 case TYPE_IOBAR:
129 msg_pdbg("I/O\n");
130#if __FLASHROM_HAVE_OUTB__
131 if (!(supported_cycles & PCI_COMMAND_IO)) {
132 msg_perr("I/O BAR access requested, but device has I/O space accesses disabled.\n");
133 /* TODO: Abort here? */
134 }
135#else
136 msg_perr("I/O BAR access requested, but flashrom does not support I/O BAR access on this "
137 "platform (yet).\n");
138#endif
139 addr &= PCI_BASE_ADDRESS_IO_MASK;
140 break;
141 case TYPE_ROMBAR:
142 msg_pdbg("ROM\n");
143 /* Not sure if this check is needed. */
144 if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
145 msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
146 /* TODO: Abort here? */
147 }
148 addr &= PCI_ROM_ADDRESS_MASK;
149 break;
150 case TYPE_UNKNOWN:
151 msg_perr("BAR type unknown, please report a bug at flashrom@flashrom.org\n");
152 }
153
154 return (uintptr_t)addr;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000155}
156
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000157uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000158{
159 struct pci_dev *dev;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000160 struct pci_filter filter;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000161 char *pcidev_bdf;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000162 char *msg = NULL;
163 int found = 0;
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +0000164 int i;
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +0000165 uintptr_t addr = 0, curaddr = 0;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000166
167 pacc = pci_alloc(); /* Get the pci_access structure */
168 pci_init(pacc); /* Initialize the PCI library */
169 pci_scan_bus(pacc); /* We want to get the list of devices */
170 pci_filter_init(pacc, &filter);
171
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000172 /* Filter by bb:dd.f (if supplied by the user). */
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000173 pcidev_bdf = extract_programmer_param("pci");
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000174 if (pcidev_bdf != NULL) {
175 if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000176 msg_perr("Error: %s\n", msg);
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000177 exit(1);
178 }
179 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000180 free(pcidev_bdf);
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000181
182 for (dev = pacc->devices; dev; dev = dev->next) {
183 if (pci_filter_match(&filter, dev)) {
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +0000184 /* Check against list of supported devices. */
185 for (i = 0; devs[i].device_name != NULL; i++)
186 if ((dev->vendor_id == devs[i].vendor_id) &&
187 (dev->device_id == devs[i].device_id))
188 break;
189 /* Not supported, try the next one. */
190 if (devs[i].device_name == NULL)
191 continue;
192
193 msg_pdbg("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name,
194 devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev,
195 dev->func);
196 if (devs[i].status == NT)
197 msg_pinfo("===\nThis PCI device is UNTESTED. Please report the 'flashrom -p "
198 "xxxx' output \n"
199 "to flashrom@flashrom.org if it works for you. Please add the name "
200 "of your\n"
201 "PCI device to the subject. Thank you for your help!\n===\n");
202
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000203 /* FIXME: We should count all matching devices, not
204 * just those with a valid BAR.
205 */
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +0000206 if ((addr = pcidev_readbar(dev, bar)) != 0) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000207 curaddr = addr;
208 pcidev_dev = dev;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000209 found++;
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000210 }
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000211 }
212 }
213
214 /* Only continue if exactly one supported PCI dev has been found. */
215 if (found == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000216 msg_perr("Error: No supported PCI device found.\n");
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000217 exit(1);
218 } else if (found > 1) {
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +0000219 msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f' \n"
220 "to explicitly select the card with the given BDF (PCI bus, device, function).\n");
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000221 exit(1);
222 }
223
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000224 return curaddr;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000225}
226
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000227void print_supported_pcidevs(const struct pcidev_status *devs)
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000228{
229 int i;
230
Carl-Daniel Hailfingera73fb492010-10-06 23:48:34 +0000231 msg_pinfo("PCI devices:\n");
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000232 for (i = 0; devs[i].vendor_name != NULL; i++) {
Carl-Daniel Hailfingeref697832010-10-07 22:21:45 +0000233 msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000234 devs[i].device_name, devs[i].vendor_id,
235 devs[i].device_id,
236 (devs[i].status == NT) ? " (untested)" : "");
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000237 }
238}
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000239
240enum pci_write_type {
241 pci_write_type_byte,
242 pci_write_type_word,
243 pci_write_type_long,
244};
245
246struct undo_pci_write_data {
247 struct pci_dev dev;
248 int reg;
249 enum pci_write_type type;
250 union {
251 uint8_t bytedata;
252 uint16_t worddata;
253 uint32_t longdata;
254 };
255};
256
David Hendricks8bb20212011-06-14 01:35:36 +0000257int undo_pci_write(void *p)
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000258{
259 struct undo_pci_write_data *data = p;
260 msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n",
261 data->dev.bus, data->dev.dev, data->dev.func, data->reg);
262 switch (data->type) {
263 case pci_write_type_byte:
264 pci_write_byte(&data->dev, data->reg, data->bytedata);
265 break;
266 case pci_write_type_word:
267 pci_write_word(&data->dev, data->reg, data->worddata);
268 break;
269 case pci_write_type_long:
270 pci_write_long(&data->dev, data->reg, data->longdata);
271 break;
272 }
273 /* p was allocated in register_undo_pci_write. */
274 free(p);
David Hendricks8bb20212011-06-14 01:35:36 +0000275 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000276}
277
278#define register_undo_pci_write(a, b, c) \
279{ \
280 struct undo_pci_write_data *undo_pci_write_data; \
281 undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \
Stefan Tauner269de352011-07-12 22:35:21 +0000282 if (!undo_pci_write_data) { \
283 msg_gerr("Out of memory!\n"); \
284 exit(1); \
285 } \
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000286 undo_pci_write_data->dev = *a; \
287 undo_pci_write_data->reg = b; \
288 undo_pci_write_data->type = pci_write_type_##c; \
289 undo_pci_write_data->c##data = pci_read_##c(dev, reg); \
290 register_shutdown(undo_pci_write, undo_pci_write_data); \
291}
292
293#define register_undo_pci_write_byte(a, b) register_undo_pci_write(a, b, byte)
294#define register_undo_pci_write_word(a, b) register_undo_pci_write(a, b, word)
295#define register_undo_pci_write_long(a, b) register_undo_pci_write(a, b, long)
296
297int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data)
298{
299 register_undo_pci_write_byte(dev, reg);
300 return pci_write_byte(dev, reg, data);
301}
302
303int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data)
304{
305 register_undo_pci_write_word(dev, reg);
306 return pci_write_word(dev, reg, data);
307}
308
309int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data)
310{
311 register_undo_pci_write_long(dev, reg);
312 return pci_write_long(dev, reg, data);
313}