blob: eac056e09e331139fec7bb20758916b676a09066 [file] [log] [blame]
Uwe Hermannddd5c9e2010-02-21 21:17:00 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000023#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000024#include "programmer.h"
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000025
26#define BIOS_ROM_ADDR 0x90
27#define BIOS_ROM_DATA 0x94
28
29#define REG_FLASH_ACCESS 0x58
30
31#define PCI_VENDOR_ID_HPT 0x1103
32
Carl-Daniel Hailfingera73fb492010-10-06 23:48:34 +000033const struct pcidev_status ata_hpt[] = {
Michael Karcher84486392010-02-24 00:04:40 +000034 {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
35 {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
36 {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000037
38 {},
39};
40
41int atahpt_init(void)
42{
43 uint32_t reg32;
44
45 get_io_perms();
46
47 io_base_addr = pcidev_init(PCI_VENDOR_ID_HPT, PCI_BASE_ADDRESS_4,
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000048 ata_hpt);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000049
50 /* Enable flash access. */
51 reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
52 reg32 |= (1 << 24);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000053 rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000054
55 buses_supported = CHIP_BUSTYPE_PARALLEL;
56
57 return 0;
58}
59
60int atahpt_shutdown(void)
61{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000062 /* Flash access is disabled automatically by PCI restore. */
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000063 pci_cleanup(pacc);
64 release_io_perms();
65 return 0;
66}
67
68void atahpt_chip_writeb(uint8_t val, chipaddr addr)
69{
70 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
71 OUTB(val, io_base_addr + BIOS_ROM_DATA);
72}
73
74uint8_t atahpt_chip_readb(const chipaddr addr)
75{
76 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
77 return INB(io_base_addr + BIOS_ROM_DATA);
78}