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review.sourcearcade.org / flashprog / f4a673b0cf819fb0ff7e2d446b52f50c10f42a2b / . / m29f400bt.h
blob: 965f731b8c317d4591264af617c58e9b0a4f04c2 [file] [log] [blame]
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000[diff] [blame]1#ifndef __M29F400BT_H__
2#define __M29F400BT_H__ 1
3
4#include <stdio.h>
5
Ollie Lho761bf1b2004-03-20 16:46:10 +0000[diff] [blame]6extern int probe_m29f400bt(struct flashchip *flash);
7extern int erase_m29f400bt(struct flashchip *flash);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000[diff] [blame]8extern int block_erase_m29f400bt(volatile uint8_t *bios,
9 volatile uint8_t *dst);
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]10extern int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000[diff] [blame]11extern int write_linuxbios_m29f400bt(struct flashchip *flash, uint8_t *buf);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]12
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]13extern __inline__ void toggle_ready_m29f400bt(volatile uint8_t *dst)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]14{
15 unsigned int i = 0;
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]16 uint8_t tmp1, tmp2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]17
18 tmp1 = *dst & 0x40;
19
20 while (i++ < 0xFFFFFF) {
21 tmp2 = *dst & 0x40;
22 if (tmp1 == tmp2) {
23 break;
24 }
25 tmp1 = tmp2;
26 }
27}
28
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]29extern __inline__ void data_polling_m29f400bt(volatile uint8_t *dst,
30 uint8_t data)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]31{
32 unsigned int i = 0;
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]33 uint8_t tmp;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]34
35 data &= 0x80;
36
37 while (i++ < 0xFFFFFF) {
38 tmp = *dst & 0x80;
39 if (tmp == data) {
40 break;
41 }
42 }
43}
44
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]45extern __inline__ void protect_m29f400bt(volatile uint8_t *bios)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]46{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000[diff] [blame]47 *(volatile uint8_t *)(bios + 0xAAA) = 0xAA;
48 *(volatile uint8_t *)(bios + 0x555) = 0x55;
49 *(volatile uint8_t *)(bios + 0xAAA) = 0xA0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]50
51 usleep(200);
52}
53
Uwe Hermanna7e05482007-05-09 10:17:44 +0000[diff] [blame]54extern __inline__ void write_page_m29f400bt(volatile uint8_t *bios,
55 uint8_t *src,
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]56 volatile uint8_t *dst,
Ollie Lho761bf1b2004-03-20 16:46:10 +0000[diff] [blame]57 int page_size)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]58{
59 int i;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000[diff] [blame]60
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]61 for (i = 0; i < page_size; i++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000[diff] [blame]62 *(volatile uint8_t *)(bios + 0xAAA) = 0xAA;
63 *(volatile uint8_t *)(bios + 0x555) = 0x55;
64 *(volatile uint8_t *)(bios + 0xAAA) = 0xA0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]65
66 /* transfer data from source to destination */
67 *dst = *src;
68 //*(volatile char *) (bios) = 0xF0;
69 //usleep(5);
70 toggle_ready_m29f400bt(dst);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000[diff] [blame]71 printf
72 ("Value in the flash at address %p = %#x, want %#x\n",
Ollie Lho184a4042005-11-26 21:55:36 +0000[diff] [blame]73 (uint8_t *) (dst - bios), *dst, *src);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000[diff] [blame]74 dst++;
75 src++;
76 }
77
78}
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000[diff] [blame]79
Ollie Lho761bf1b2004-03-20 16:46:10 +0000[diff] [blame]80#endif /* !__M29F400BT_H__ */