blob: 6f0097f2e681d68640c8b46210225f0ee560e0ee [file] [log] [blame]
Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
23#include <sys/types.h>
24#include "flash.h"
25
26#define PCI_VENDOR_ID_REALTEK 0x10ec
27#define PCI_VENDOR_ID_SMC1211 0x1113
28
29#define BIOS_ROM_ADDR 0xD4
30#define BIOS_ROM_DATA 0xD7
31
32struct pcidev_status nics_realtek[] = {
33 {0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"},
34 {},
35};
36
37struct pcidev_status nics_realteksmc1211[] = {
38 {0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"},
39 {}
40};
41
42
43int nicrealtek_init(void)
44{
45 get_io_perms();
46 io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0,
47 nics_realtek, programmer_param);
48
49 buses_supported = CHIP_BUSTYPE_PARALLEL;
50
51 return 0;
52}
53
54
55int nicsmc1211_init(void)
56{
57 get_io_perms();
58 io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0,
59 nics_realteksmc1211, programmer_param);
60
61 buses_supported = CHIP_BUSTYPE_PARALLEL;
62
63 return 0;
64}
65
66int nicrealtek_shutdown(void)
67{
68 free(programmer_param);
69 pci_cleanup(pacc);
70 release_io_perms();
71 return 0;
72}
73
74void nicrealtek_chip_writeb(uint8_t val, chipaddr addr)
75{
76 OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR);
77 OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR);
78}
79
80uint8_t nicrealtek_chip_readb(const chipaddr addr)
81
82{
83 uint8_t val=INB(io_base_addr + BIOS_ROM_DATA);
84 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), io_base_addr + BIOS_ROM_ADDR);
85 val=INB(io_base_addr + BIOS_ROM_DATA);
86 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), io_base_addr + BIOS_ROM_ADDR);
87 return val ;
88
89}