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Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __FLASHCHIPS_H__
25#define __FLASHCHIPS_H__ 1
26
27/*
28 * Please keep this list sorted alphabetically by manufacturer. The first
29 * entry of each section should be the manufacturer ID, followed by the
30 * list of devices from that manufacturer (sorted by device IDs).
31 *
32 * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
33 * continuation code.
34 * SPI parts have 16-bit device IDs if they support RDID.
35 */
36
37#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
38
39#define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
40
41#define AMD_ID 0x01 /* AMD */
Uwe Hermanna8b37272009-06-19 15:54:39 +000042#define AM_29F010B 0x20 /* Same as Am29F010A */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000043#define AM_29F002BT 0xB0
44#define AM_29F002BB 0x34
45#define AM_29F040B 0xA4
46#define AM_29F080B 0xD5
47#define AM_29LV040B 0x4F
48#define AM_29LV081B 0x38
49#define AM_29F016D 0xAD
50
51#define AMIC_ID 0x7F37 /* AMIC */
52#define AMIC_ID_NOPREFIX 0x37 /* AMIC */
53#define AMIC_A25L40P 0x2013
54#define AMIC_A29002B 0x0d
55#define AMIC_A29002T 0x8c
56#define AMIC_A29040B 0x86
57#define AMIC_A49LF040A 0x9d
58
59/* This chip vendor/device ID is probably a misinterpreted LHA header. */
60#define ASD_ID 0x25 /* ASD, not listed in JEP106W */
61#define ASD_AE49F2008 0x52
62
63#define ATMEL_ID 0x1F /* Atmel */
64#define AT_25DF021 0x4300
65#define AT_25DF041A 0x4401
66#define AT_25DF081 0x4502
67#define AT_25DF161 0x4602
68#define AT_25DF321 0x4700 /* also 26DF321 */
69#define AT_25DF321A 0x4701
70#define AT_25DF641 0x4800
71#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */
72#define AT_25F512B 0x6500
73#define AT_25FS010 0x6601
74#define AT_25FS040 0x6604
75#define AT_26DF041 0x4400
76#define AT_26DF081 0x4500 /* guessed, no datasheet available */
77#define AT_26DF081A 0x4501
78#define AT_26DF161 0x4600
79#define AT_26DF161A 0x4601
80#define AT_26DF321 0x4700 /* also 25DF321 */
81#define AT_26F004 0x0400
82#define AT_29C040A 0xA4
83#define AT_29C010A 0xD5
84#define AT_29C020 0xDA
85#define AT_29C512 0x5D
86#define AT_45BR3214B /* No ID available */
87#define AT_45CS1282 0x2920
88#define AT_45D011 /* No ID available */
89#define AT_45D021A /* No ID available */
90#define AT_45D041A /* No ID available */
91#define AT_45D081A /* No ID available */
92#define AT_45D161 /* No ID available */
93#define AT_45DB011 /* No ID available */
94#define AT_45DB011B /* No ID available */
95#define AT_45DB011D 0x2200
96#define AT_45DB021A /* No ID available */
97#define AT_45DB021B /* No ID available */
98#define AT_45DB021D 0x2300
99#define AT_45DB041A /* No ID available */
100#define AT_45DB041D 0x2400
101#define AT_45DB081A /* No ID available */
102#define AT_45DB081D 0x2500
103#define AT_45DB161 /* No ID available */
104#define AT_45DB161B /* No ID available */
105#define AT_45DB161D 0x2600
106#define AT_45DB321 /* No ID available */
107#define AT_45DB321B /* No ID available */
108#define AT_45DB321C 0x2700
109#define AT_45DB321D 0x2701 /* Buggy data sheet */
110#define AT_45DB642 /* No ID available */
111#define AT_45DB642D 0x2800
112#define AT_49BV512 0x03
113#define AT_49F002N 0x07 /* for AT49F002(N) */
114#define AT_49F002NT 0x08 /* for AT49F002(N)T */
115
116#define CATALYST_ID 0x31 /* Catalyst */
117
118#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
119#define EMST_F49B002UA 0x00
120
121/*
122 * EN25 chips are SPI, first byte of device ID is memory type,
123 * second byte of device ID is log(bitsize)-9.
124 * Vendor and device ID of EN29 series are both prefixed with 0x7F, which
125 * is the continuation code for IDs in bank 2.
126 * Vendor ID of EN25 series is NOT prefixed with 0x7F, this results in
127 * a collision with Mitsubishi. Mitsubishi once manufactured flash chips.
128 * Let's hope they are not manufacturing SPI flash chips as well.
129 */
130#define EON_ID 0x7F1C /* EON Silicon Devices */
131#define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */
132#define EN_25B05 0x2010 /* also P05, 2^19 kbit or 2^16 kByte */
133#define EN_25B10 0x2011 /* also P10 */
134#define EN_25B20 0x2012 /* also P20 */
135#define EN_25B40 0x2013 /* also P40 */
136#define EN_25B80 0x2014 /* also P80 */
137#define EN_25B16 0x2015 /* also P16 */
138#define EN_25B32 0x2016 /* also P32 */
139#define EN_25B64 0x2017 /* also P64 */
140#define EN_25D16 0x3015
141#define EN_25F05 0x3110
142#define EN_25F10 0x3111
143#define EN_25F20 0x3112
144#define EN_25F40 0x3113
145#define EN_25F80 0x3114
146#define EN_25F16 0x3115
147#define EN_25F32 0x3116
148#define EN_29F512 0x7F21
149#define EN_29F010 0x7F20
150#define EN_29F040A 0x7F04
151#define EN_29LV010 0x7F6E
152#define EN_29LV040A 0x7F4F /* EN_29LV040(A) */
153#define EN_29F002T 0x7F92 /* Also EN29F002A */
154#define EN_29F002B 0x7F97 /* Also EN29F002AN */
155
156#define FUJITSU_ID 0x04 /* Fujitsu */
157#define MBM29F400BC 0xAB
158#define MBM29F400TC 0x23
159#define MBM29F004BC 0x7B
160#define MBM29F004TC 0x77
161
162#define HYUNDAI_ID 0xAD /* Hyundai */
163
164#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
165#define IM_29F004B 0xAE
166#define IM_29F004T 0xAF
167
168#define INTEL_ID 0x89 /* Intel */
169#define I_82802AB 0xAD
170#define I_82802AC 0xAC
171#define P28F001BXT 0x94 /* 28F001BX-T */
172#define P28F001BXB 0x95 /* 28F001BX-B */
173
174#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */
175
176/*
177 * MX25 chips are SPI, first byte of device ID is memory type,
178 * second byte of device ID is log(bitsize)-9.
179 * Generalplus SPI chips seem to be compatible with Macronix
180 * and use the same set of IDs.
181 */
182#define MX_ID 0xC2 /* Macronix (MX) */
183#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
184#define MX_25L1005 0x2011
185#define MX_25L2005 0x2012
186#define MX_25L4005 0x2013 /* MX25L4005{,A} */
187#define MX_25L8005 0x2014
188#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */
189#define MX_25L3205 0x2016 /* MX25L3205{,A} */
190#define MX_25L6405 0x2017 /* MX25L3205{,D} */
191#define MX_25L12805 0x2018 /* MX25L12805 */
192#define MX_25L1635D 0x2415
193#define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */
194#define MX_29F002B 0x34
195#define MX_29F002T 0xB0
196#define MX_29LV002CB 0x5A
197#define MX_29LV002CT 0x59
198#define MX_29LV004CB 0xB6
199#define MX_29LV004CT 0xB5
200#define MX_29LV008CB 0x37
201#define MX_29LV008CT 0x3E
202#define MX_29F040C 0xA4
203#define MX_29F200CB 0x57
204#define MX_29F200CT 0x51
205#define MX_29F400CB 0xAB
206#define MX_29F400CT 0x23
207#define MX_29LV040C 0x4F
208#define MX_29LV128DB 0x7A
209#define MX_29LV128DT 0x7E
210#define MX_29LV160DB 0x49 /* Same as MX29LV161DB/MX29LV160CB */
211#define MX_29LV160DT 0xC4 /* Same as MX29LV161DT/MX29LV160CT */
212#define MX_29LV320DB 0xA8 /* Same as MX29LV321DB */
213#define MX_29LV320DT 0xA7 /* Same as MX29LV321DT */
214#define MX_29LV400CB 0xBA
215#define MX_29LV400CT 0xB9
216#define MX_29LV800CB 0x5B
217#define MX_29LV800CT 0xDA
218#define MX_29LV640DB 0xCB /* Same as MX29LV640EB */
219#define MX_29LV640DT 0xC9 /* Same as MX29LV640ET */
220#define MX_29SL402CB 0xF1
221#define MX_29SL402CT 0x70
222#define MX_29SL800CB 0x6B /* Same as MX29SL802CB */
223#define MX_29SL800CT 0xEA /* Same as MX29SL802CT */
224
225/*
226 * Programmable Micro Corp is listed in JEP106W in bank 2, so it should
227 * have a 0x7F continuation code prefix.
228 */
229#define PMC_ID 0x7F9D /* PMC */
230#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
231#define PMC_25LV512 0x7B
232#define PMC_25LV010 0x7C
233#define PMC_25LV020 0x7D
234#define PMC_25LV040 0x7E
235#define PMC_25LV080B 0x13
236#define PMC_25LV016B 0x14
237#define PMC_29F002T 0x1D
238#define PMC_29F002B 0x2D
239#define PMC_39LV512 0x1B
240#define PMC_39F010 0x1C /* also Pm39LV010 */
241#define PMC_39LV020 0x3D
242#define PMC_39LV040 0x3E
243#define PMC_39F020 0x4D
244#define PMC_39F040 0x4E
245#define PMC_49FL002 0x6D
246#define PMC_49FL004 0x6E
247
248#define SHARP_ID 0xB0 /* Sharp */
249#define SHARP_LHF00L04 0xCF
250
251/*
252 * Spansion was previously a joint venture of AMD and Fujitsu.
253 * S25 chips are SPI. The first device ID byte is memory type and
254 * the second device ID byte is memory capacity.
255 */
256#define SPANSION_ID 0x01 /* Spansion */
257#define SPANSION_S25FL016A 0x0214
258
259/*
260 * SST25 chips are SPI, first byte of device ID is memory type, second
261 * byte of device ID is related to log(bitsize) at least for some chips.
262 */
263#define SST_ID 0xBF /* SST */
264#define SST_25WF512 0x2501
265#define SST_25WF010 0x2502
266#define SST_25WF020 0x2503
267#define SST_25WF040 0x2504
268#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */
269#define SST_25VF010_REMS 0x49 /* REMS or RES opcode */
270#define SST_25VF020_REMS 0x43 /* REMS or RES opcode */
271#define SST_25VF040_REMS 0x44 /* REMS or RES opcode */
272#define SST_25VF040B 0x258D
273#define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */
274#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */
275#define SST_25VF080B 0x258E
276#define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */
277#define SST_25VF016B 0x2541
278#define SST_25VF032B 0x254A
279#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */
280#define SST_26VF016 0x2601
281#define SST_26VF032 0x2602
282#define SST_27SF512 0xA4
283#define SST_27SF010 0xA5
284#define SST_27SF020 0xA6
285#define SST_27VF010 0xA9
286#define SST_27VF020 0xAA
287#define SST_28SF040 0x04
288#define SST_29EE512 0x5D
289#define SST_29EE010 0x07
290#define SST_29LE010 0x08 /* also SST29VE010 */
291#define SST_29EE020A 0x10 /* also SST29EE020 */
292#define SST_29LE020 0x12 /* also SST29VE020 */
293#define SST_29SF020 0x24
294#define SST_29VF020 0x25
295#define SST_29SF040 0x13
296#define SST_29VF040 0x14
297#define SST_39SF010 0xB5
298#define SST_39SF020 0xB6
299#define SST_39SF040 0xB7
300#define SST_39VF512 0xD4
301#define SST_39VF010 0xD5
302#define SST_39VF020 0xD6
303#define SST_39VF040 0xD7
304#define SST_39VF080 0xD8
305#define SST_49LF040B 0x50
306#define SST_49LF040 0x51
307#define SST_49LF020 0x61
308#define SST_49LF020A 0x52
309#define SST_49LF080A 0x5B
310#define SST_49LF002A 0x57
311#define SST_49LF003A 0x1B
312#define SST_49LF004A 0x60
313#define SST_49LF008A 0x5A
314#define SST_49LF004C 0x54
315#define SST_49LF008C 0x59
316#define SST_49LF016C 0x5C
317#define SST_49LF160C 0x4C
318
319/*
320 * ST25P chips are SPI, first byte of device ID is memory type, second
321 * byte of device ID is related to log(bitsize) at least for some chips.
322 */
323#define ST_ID 0x20 /* ST / SGS/Thomson */
324#define ST_M25P05A 0x2010
325#define ST_M25P10A 0x2011
326#define ST_M25P20 0x2012
327#define ST_M25P40 0x2013
328#define ST_M25P40_RES 0x12
329#define ST_M25P80 0x2014
330#define ST_M25P16 0x2015
331#define ST_M25P32 0x2016
332#define ST_M25P64 0x2017
333#define ST_M25P128 0x2018
334#define ST_M25PE10 0x8011
335#define ST_M25PE20 0x8012
336#define ST_M25PE40 0x8013
337#define ST_M25PE80 0x8014
338#define ST_M25PE16 0x8015
339#define ST_M50FLW040A 0x08
340#define ST_M50FLW040B 0x28
341#define ST_M50FLW080A 0x80
342#define ST_M50FLW080B 0x81
343#define ST_M50FW002 0x29
344#define ST_M50FW040 0x2C
345#define ST_M50FW080 0x2D
346#define ST_M50FW016 0x2E
347#define ST_M50LPW116 0x30
348#define ST_M29F002B 0x34
349#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */
350#define ST_M29F400BT 0xD5
351#define ST_M29F040B 0xE2
352#define ST_M29W010B 0x23
353#define ST_M29W040B 0xE3
354
355#define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */
356#define S29C51001T 0x01
357#define S29C51002T 0x02
358#define S29C51004T 0x03
359#define S29C31004T 0x63
360
361#define TI_ID 0x97 /* Texas Instruments */
362#define TI_OLD_ID 0x01 /* TI chips from last century */
363#define TI_TMS29F002RT 0xB0
364#define TI_TMS29F002RB 0x34
365
366/*
367 * W25X chips are SPI, first byte of device ID is memory type, second
368 * byte of device ID is related to log(bitsize).
369 */
370#define WINBOND_ID 0xDA /* Winbond */
371#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */
372#define W_25X10 0x3011
373#define W_25X20 0x3012
374#define W_25X40 0x3013
375#define W_25X80 0x3014
376#define W_25X16 0x3015
377#define W_25X32 0x3016
378#define W_25X64 0x3017
379#define W_29C011 0xC1
380#define W_29C020C 0x45
381#define W_29C040P 0x46
382#define W_29EE011 0xC1
383#define W_39V040FA 0x34
384#define W_39V040A 0x3D
385#define W_39V040B 0x54
386#define W_39V040C 0x50
387#define W_39V080A 0xD0
388#define W_39V080FA 0xD3
389#define W_39V080FA_DM 0x93
390#define W_49F002U 0x0B
391#define W_49V002A 0xB0
392#define W_49V002FA 0x32
393
394#endif /* !FLASHCHIPS_H */