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review.sourcearcade.org / flashprog / eb75ced3494d97a9d424b37f62ca304375bd9798 / . / gfxnvidia.c
blob: ec41279d69a06ab19289b6ba75344f3a554ad169 [file] [log] [blame]
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
23#include <sys/types.h>
24#include "flash.h"
25
26#define PCI_VENDOR_ID_NVIDIA 0x10de
27
28uint8_t *nvidia_bar;
29
30struct pcidev_status gfx_nvidia[] = {
Michael Karcher84486392010-02-24 00:04:40 +0000[diff] [blame]31 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
32 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
33 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
34 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
35 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
36 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
37 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
38 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
39 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
40 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
41 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
42 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
43 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
44 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
45 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
46 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
47 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
48 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
49 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
50 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
51 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
52 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
53 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]54
55 {},
56};
57
58int gfxnvidia_init(void)
59{
60 uint32_t reg32;
61
62 get_io_perms();
63
64 io_base_addr = pcidev_init(PCI_VENDOR_ID_NVIDIA, PCI_BASE_ADDRESS_0,
65 gfx_nvidia, programmer_param);
66 io_base_addr += 0x300000;
Sean Nelson8e5e73e2010-01-09 23:54:05 +0000[diff] [blame]67 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]68
69 /* Allow access to flash interface (will disable screen). */
70 reg32 = pci_read_long(pcidev_dev, 0x50);
71 reg32 &= ~(1 << 0);
72 pci_write_long(pcidev_dev, 0x50, reg32);
73
74 nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024);
75
76 buses_supported = CHIP_BUSTYPE_PARALLEL;
77
78 return 0;
79}
80
81int gfxnvidia_shutdown(void)
82{
83 uint32_t reg32;
84
85 /* Disallow access to flash interface (and re-enable screen). */
86 reg32 = pci_read_long(pcidev_dev, 0x50);
87 reg32 |= (1 << 0);
88 pci_write_long(pcidev_dev, 0x50, reg32);
89
90 free(programmer_param);
91 pci_cleanup(pacc);
92 release_io_perms();
93 return 0;
94}
95
96void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr)
97{
98 mmio_writeb(val, nvidia_bar + addr);
99}
100
101uint8_t gfxnvidia_chip_readb(const chipaddr addr)
102{
103 return mmio_readb(nvidia_bar + addr);
104}