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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/*
21 * Contains the generic SPI framework
22 */
23
24#include <stdio.h>
25#include <pci/pci.h>
26#include <stdint.h>
27#include <string.h>
28#include "flash.h"
29
30#define ITE_SUPERIO_PORT1 0x2e
31#define ITE_SUPERIO_PORT2 0x4e
32
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000033/* Read Electronic ID */
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034#define JEDEC_RDID {0x9f}
35#define JEDEC_RDID_OUTSIZE 0x01
36#define JEDEC_RDID_INSIZE 0x03
37
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000038/* Write Enable */
39#define JEDEC_WREN {0x06}
40#define JEDEC_WREN_OUTSIZE 0x01
41#define JEDEC_WREN_INSIZE 0x00
42
43/* Write Disable */
44#define JEDEC_WRDI {0x04}
45#define JEDEC_WRDI_OUTSIZE 0x01
46#define JEDEC_WRDI_INSIZE 0x00
47
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +000048/* Chip Erase 0x60 is supported by Macronix/SST chips. */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +000049#define JEDEC_CE_60 {0x60};
50#define JEDEC_CE_60_OUTSIZE 0x01
51#define JEDEC_CE_60_INSIZE 0x00
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000052
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +000053/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
54#define JEDEC_CE_C7 {0xc7};
55#define JEDEC_CE_C7_OUTSIZE 0x01
56#define JEDEC_CE_C7_INSIZE 0x00
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000057
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +000058/* Block Erase 0x52 is supported by SST chips. */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +000059#define JEDEC_BE_52 {0x52};
60#define JEDEC_BE_52_OUTSIZE 0x04
61#define JEDEC_BE_52_INSIZE 0x00
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +000062
63/* Block Erase 0xd8 is supported by EON/Macronix chips. */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +000064#define JEDEC_BE_D8 {0xd8};
65#define JEDEC_BE_D8_OUTSIZE 0x04
66#define JEDEC_BE_D8_INSIZE 0x00
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +000067
68/* Sector Erase 0x20 is supported by Macronix/SST chips. */
69#define JEDEC_SE {0x20};
70#define JEDEC_SE_OUTSIZE 0x04
71#define JEDEC_SE_INSIZE 0x00
72
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000073/* Read Status Register */
74#define JEDEC_RDSR {0x05};
75#define JEDEC_RDSR_OUTSIZE 0x01
76#define JEDEC_RDSR_INSIZE 0x01
77#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
78
79uint16_t it8716f_flashport = 0;
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000080
81/* Generic Super I/O helper functions */
82uint8_t regval(uint16_t port, uint8_t reg)
83{
84 outb(reg, port);
85 return inb(port + 1);
86}
87
88void regwrite(uint16_t port, uint8_t reg, uint8_t val)
89{
90 outb(reg, port);
91 outb(val, port + 1);
92}
93
94/* Helper functions for most recent ITE IT87xx Super I/O chips */
95#define CHIP_ID_BYTE1_REG 0x20
96#define CHIP_ID_BYTE2_REG 0x21
97static void enter_conf_mode_ite(uint16_t port)
98{
99 outb(0x87, port);
100 outb(0x01, port);
101 outb(0x55, port);
102 if (port == ITE_SUPERIO_PORT1)
103 outb(0x55, port);
104 else
105 outb(0xaa, port);
106}
107
108static void exit_conf_mode_ite(uint16_t port)
109{
110 regwrite(port, 0x02, 0x02);
111}
112
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000113static uint16_t find_ite_spi_flash_port(uint16_t port)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000114{
115 uint8_t tmp = 0;
116 uint16_t id, flashport = 0;
117
118 enter_conf_mode_ite(port);
119
120 id = regval(port, CHIP_ID_BYTE1_REG) << 8;
121 id |= regval(port, CHIP_ID_BYTE2_REG);
122
123 /* TODO: Handle more IT87xx if they support flash translation */
124 if (id == 0x8716) {
125 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
126 tmp = regval(port, 0x24) & 0xFE;
127 printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
128 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
129 printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
130 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
131 printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
132 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
133 printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
134 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
135 printf("LPC write to serial flash %sabled\n",
136 (tmp & 1 << 4) ? "en" : "dis");
137 printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
138 /* LDN 0x7, reg 0x64/0x65 */
139 regwrite(port, 0x07, 0x7);
140 flashport = regval(port, 0x64) << 8;
141 flashport |= regval(port, 0x65);
142 }
143 exit_conf_mode_ite(port);
144 return flashport;
145}
146
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000147int it87xx_probe_spi_flash(const char *name)
148{
149 it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
150 if (!it8716f_flashport)
151 it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
152 return (!it8716f_flashport);
153}
154
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000155/* The IT8716F only supports commands with length 1,2,4,5 bytes including
156 command byte and can not read more than 3 bytes from the device.
157 This function expects writearr[0] to be the first byte sent to the device,
158 whereas the IT8716F splits commands internally into address and non-address
159 commands with the address in inverse wire order. That's why the register
160 ordering in case 4 and 5 may seem strange. */
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000161static int it8716f_spi_command(uint16_t port, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000162{
163 uint8_t busy, writeenc;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000164 int i;
165
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000166 do {
167 busy = inb(port) & 0x80;
168 } while (busy);
169 if (readcnt > 3) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000170 printf("%s called with unsupported readcnt %i.\n",
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000171 __FUNCTION__, readcnt);
172 return 1;
173 }
174 switch (writecnt) {
175 case 1:
176 outb(writearr[0], port + 1);
177 writeenc = 0x0;
178 break;
179 case 2:
180 outb(writearr[0], port + 1);
181 outb(writearr[1], port + 7);
182 writeenc = 0x1;
183 break;
184 case 4:
185 outb(writearr[0], port + 1);
186 outb(writearr[1], port + 4);
187 outb(writearr[2], port + 3);
188 outb(writearr[3], port + 2);
189 writeenc = 0x2;
190 break;
191 case 5:
192 outb(writearr[0], port + 1);
193 outb(writearr[1], port + 4);
194 outb(writearr[2], port + 3);
195 outb(writearr[3], port + 2);
196 outb(writearr[4], port + 7);
197 writeenc = 0x3;
198 break;
199 default:
Uwe Hermanna502dce2007-10-17 23:55:15 +0000200 printf("%s called with unsupported writecnt %i.\n",
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000201 __FUNCTION__, writecnt);
202 return 1;
203 }
204 /* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note:
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000205 * We can't use writecnt directly, but have to use a strange encoding.
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000206 */
207 outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
208 do {
209 busy = inb(port) & 0x80;
210 } while (busy);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000211
212 for (i = 0; i < readcnt; i++) {
213 readarr[i] = inb(port + 5 + i);
214 }
215
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000216 return 0;
217}
218
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000219int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000220{
221 if (it8716f_flashport)
222 return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr);
223 printf("%s called, but no SPI chipset detected\n", __FUNCTION__);
224 return 1;
225}
226
227static int generic_spi_rdid(unsigned char *readarr)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000228{
229 const unsigned char cmd[] = JEDEC_RDID;
230
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000231 if (generic_spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr))
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000232 return 1;
Uwe Hermanna502dce2007-10-17 23:55:15 +0000233 printf("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000234 return 0;
235}
236
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000237void generic_spi_write_enable()
238{
239 const unsigned char cmd[] = JEDEC_WREN;
240
241 /* Send WREN (Write Enable) */
242 generic_spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL);
243
244}
245
246void generic_spi_write_disable()
247{
248 const unsigned char cmd[] = JEDEC_WRDI;
249
250 /* Send WRDI (Write Disable) */
251 generic_spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL);
252}
253
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000254int probe_spi(struct flashchip *flash)
255{
256 unsigned char readarr[3];
257 uint8_t manuf_id;
258 uint16_t model_id;
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000259 if (!generic_spi_rdid(readarr)) {
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000260 manuf_id = readarr[0];
261 model_id = (readarr[1] << 8) | readarr[2];
262 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
263 if (manuf_id == flash->manufacture_id && model_id == flash->model_id)
264 return 1;
265 }
266
267 return 0;
268}
269
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000270uint8_t generic_spi_read_status_register()
271{
272 const unsigned char cmd[] = JEDEC_RDSR;
273 unsigned char readarr[1];
274
275 /* Read Status Register */
276 generic_spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr);
277 return readarr[0];
278}
279
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000280int generic_spi_chip_erase_c7(struct flashchip *flash)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000281{
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000282 const unsigned char cmd[] = JEDEC_CE_C7;
Carl-Daniel Hailfingerf5df46f2007-12-16 21:15:27 +0000283 uint8_t statusreg;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000284
Carl-Daniel Hailfingerf5df46f2007-12-16 21:15:27 +0000285 statusreg = generic_spi_read_status_register();
286 printf("chip status register before erase is %02x\n", statusreg);
287
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000288 generic_spi_write_enable();
289 /* Send CE (Chip Erase) */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000290 generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000291 /* Wait until the Write-In-Progress bit is cleared.
292 * This usually takes 1-85 s, so wait in 1 s steps.
293 */
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000294 while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
295 sleep(1);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000296 return 0;
297}
298
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000299/* Block size is usually
300 * 64k for Macronix
301 * 32k for SST
302 * 4-32k non-uniform for EON
303 */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000304int generic_spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000305{
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000306 unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8;
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000307
308 cmd[1] = (addr & 0x00ff0000) >> 16;
309 cmd[2] = (addr & 0x0000ff00) >> 8;
310 cmd[3] = (addr & 0x000000ff);
311 generic_spi_write_enable();
312 /* Send BE (Block Erase) */
Carl-Daniel Hailfinger21c78902007-12-17 14:33:32 +0000313 generic_spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000314 /* Wait until the Write-In-Progress bit is cleared.
315 * This usually takes 100-4000 ms, so wait in 100 ms steps.
316 */
317 while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
318 usleep(100 * 1000);
319 return 0;
320}
321
322/* Sector size is usually 4k, though Macronix eliteflash has 64k */
323int generic_spi_sector_erase(const struct flashchip *flash, unsigned long addr)
324{
325 unsigned char cmd[JEDEC_SE_OUTSIZE] = JEDEC_SE;
326 cmd[1] = (addr & 0x00ff0000) >> 16;
327 cmd[2] = (addr & 0x0000ff00) >> 8;
328 cmd[3] = (addr & 0x000000ff);
329
330 generic_spi_write_enable();
331 /* Send SE (Sector Erase) */
332 generic_spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL);
333 /* Wait until the Write-In-Progress bit is cleared.
334 * This usually takes 15-800 ms, so wait in 10 ms steps.
335 */
336 while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
337 usleep(10 * 1000);
338 return 0;
339}
340
341/* Page size is usually 256 bytes */
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000342void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
343 int i;
344
345 generic_spi_write_enable();
346 outb(0x06 , it8716f_flashport + 1);
347 outb((3 << 4), it8716f_flashport);
348 for (i = 0; i < 256; i++) {
349 bios[256 * block + i] = buf[256 * block + i];
350 }
351 outb(0, it8716f_flashport);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000352 /* Wait until the Write-In-Progress bit is cleared.
353 * This usually takes 1-10 ms, so wait in 1 ms steps.
354 */
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000355 while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
356 usleep(1000);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000357}
358
359void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
360{
361 if (it8716f_flashport)
362 it8716f_spi_page_program(block, buf, bios);
363}
364
365int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf) {
366 int total_size = 1024 * flash->total_size;
367 int i;
368 for (i = 0; i < total_size / 256; i++) {
369 generic_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
370 }
371 return 0;
372}
373