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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000025#include <string.h>
26#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000027#include "flashchips.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000028#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000029
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000030enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
31void *spibar = NULL;
32
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000033void spi_prettyprint_status_register(struct flashchip *flash);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000035const struct spi_programmer spi_programmer[] = {
36 { /* SPI_CONTROLLER_NONE */
37 .command = NULL,
38 .multicommand = NULL,
39 .read = NULL,
40 .write_256 = NULL,
41 },
42
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +000043#if INTERNAL_SUPPORT == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000044 { /* SPI_CONTROLLER_ICH7 */
45 .command = ich_spi_send_command,
46 .multicommand = ich_spi_send_multicommand,
47 .read = ich_spi_read,
48 .write_256 = ich_spi_write_256,
49 },
50
51 { /* SPI_CONTROLLER_ICH9 */
52 .command = ich_spi_send_command,
53 .multicommand = ich_spi_send_multicommand,
54 .read = ich_spi_read,
55 .write_256 = ich_spi_write_256,
56 },
57
58 { /* SPI_CONTROLLER_IT87XX */
59 .command = it8716f_spi_send_command,
60 .multicommand = default_spi_send_multicommand,
61 .read = it8716f_spi_chip_read,
62 .write_256 = it8716f_spi_chip_write_256,
63 },
64
65 { /* SPI_CONTROLLER_SB600 */
66 .command = sb600_spi_send_command,
67 .multicommand = default_spi_send_multicommand,
68 .read = sb600_spi_read,
69 .write_256 = sb600_spi_write_1,
70 },
71
72 { /* SPI_CONTROLLER_VIA */
73 .command = ich_spi_send_command,
74 .multicommand = ich_spi_send_multicommand,
75 .read = ich_spi_read,
76 .write_256 = ich_spi_write_256,
77 },
78
79 { /* SPI_CONTROLLER_WBSIO */
80 .command = wbsio_spi_send_command,
81 .multicommand = default_spi_send_multicommand,
82 .read = wbsio_spi_read,
83 .write_256 = wbsio_spi_write_1,
84 },
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +000085#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000086
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +000087#if FT2232_SPI_SUPPORT == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000088 { /* SPI_CONTROLLER_FT2232 */
89 .command = ft2232_spi_send_command,
90 .multicommand = default_spi_send_multicommand,
91 .read = ft2232_spi_read,
92 .write_256 = ft2232_spi_write_256,
93 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +000094#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000095
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +000096#if DUMMY_SUPPORT == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000097 { /* SPI_CONTROLLER_DUMMY */
98 .command = dummy_spi_send_command,
99 .multicommand = default_spi_send_multicommand,
100 .read = NULL,
101 .write_256 = NULL,
102 },
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000103#endif
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000104
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000105#if BUSPIRATE_SPI_SUPPORT == 1
106 { /* SPI_CONTROLLER_BUSPIRATE */
107 .command = buspirate_spi_send_command,
108 .multicommand = default_spi_send_multicommand,
109 .read = buspirate_spi_read,
110 .write_256 = spi_chip_write_1,
111 },
112#endif
113
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000114 {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000115};
116
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000117const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000118
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000119int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000120 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000121{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000122 if (!spi_programmer[spi_controller].command) {
123 fprintf(stderr, "%s called, but SPI is unsupported on this "
124 "hardware. Please report a bug.\n", __func__);
125 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000126 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000127
128 return spi_programmer[spi_controller].command(writecnt, readcnt,
129 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000130}
131
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000132int spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000133{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000134 if (!spi_programmer[spi_controller].multicommand) {
135 fprintf(stderr, "%s called, but SPI is unsupported on this "
136 "hardware. Please report a bug.\n", __func__);
137 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000138 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000139
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000140 return spi_programmer[spi_controller].multicommand(cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000141}
142
143int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
144 const unsigned char *writearr, unsigned char *readarr)
145{
146 struct spi_command cmd[] = {
147 {
148 .writecnt = writecnt,
149 .readcnt = readcnt,
150 .writearr = writearr,
151 .readarr = readarr,
152 }, {
153 .writecnt = 0,
154 .writearr = NULL,
155 .readcnt = 0,
156 .readarr = NULL,
157 }};
158
159 return spi_send_multicommand(cmd);
160}
161
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000162int default_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000163{
164 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000165 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
166 result = spi_send_command(cmds->writecnt, cmds->readcnt,
167 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000168 }
169 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000170}
171
Rudolf Marek48a85e42008-06-30 21:45:17 +0000172static int spi_rdid(unsigned char *readarr, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000173{
Uwe Hermann394131e2008-10-18 21:14:13 +0000174 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000175 int ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000176 int i;
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000177
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000178 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000179 if (ret)
180 return ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000181 printf_debug("RDID returned");
182 for (i = 0; i < bytes; i++)
183 printf_debug(" 0x%02x", readarr[i]);
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000184 printf_debug(". ");
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000185 return 0;
186}
187
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000188static int spi_rems(unsigned char *readarr)
189{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000190 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
191 uint32_t readaddr;
192 int ret;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000193
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000194 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000195 if (ret == SPI_INVALID_ADDRESS) {
196 /* Find the lowest even address allowed for reads. */
197 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
198 cmd[1] = (readaddr >> 16) & 0xff,
199 cmd[2] = (readaddr >> 8) & 0xff,
200 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000201 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000202 }
203 if (ret)
204 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000205 printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000206 return 0;
207}
208
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000209static int spi_res(unsigned char *readarr)
210{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000211 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
212 uint32_t readaddr;
213 int ret;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000214
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000215 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000216 if (ret == SPI_INVALID_ADDRESS) {
217 /* Find the lowest even address allowed for reads. */
218 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
219 cmd[1] = (readaddr >> 16) & 0xff,
220 cmd[2] = (readaddr >> 8) & 0xff,
221 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000222 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000223 }
224 if (ret)
225 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000226 printf_debug("RES returned %02x. ", readarr[0]);
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000227 return 0;
228}
229
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000230int spi_write_enable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000231{
Uwe Hermann394131e2008-10-18 21:14:13 +0000232 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000233 int result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000234
235 /* Send WREN (Write Enable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000236 result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000237
238 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000239 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000240
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000241 return result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000242}
243
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000244int spi_write_disable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000245{
Uwe Hermann394131e2008-10-18 21:14:13 +0000246 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000247
248 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000249 return spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000250}
251
Rudolf Marek48a85e42008-06-30 21:45:17 +0000252static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000253{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000254 unsigned char readarr[4];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000255 uint32_t id1;
256 uint32_t id2;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000257
Rudolf Marek48a85e42008-06-30 21:45:17 +0000258 if (spi_rdid(readarr, bytes))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000259 return 0;
260
261 if (!oddparity(readarr[0]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000262 printf_debug("RDID byte 0 parity violation. ");
Peter Stugeda4e5f32008-06-24 01:22:03 +0000263
264 /* Check if this is a continuation vendor ID */
265 if (readarr[0] == 0x7f) {
266 if (!oddparity(readarr[1]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000267 printf_debug("RDID byte 1 parity violation. ");
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000268 id1 = (readarr[0] << 8) | readarr[1];
269 id2 = readarr[2];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000270 if (bytes > 3) {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000271 id2 <<= 8;
272 id2 |= readarr[3];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000273 }
Peter Stugeda4e5f32008-06-24 01:22:03 +0000274 } else {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000275 id1 = readarr[0];
276 id2 = (readarr[1] << 8) | readarr[2];
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000277 }
278
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000279 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Peter Stugeda4e5f32008-06-24 01:22:03 +0000280
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000281 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Peter Stugeda4e5f32008-06-24 01:22:03 +0000282 /* Print the status register to tell the
283 * user about possible write protection.
284 */
285 spi_prettyprint_status_register(flash);
286
287 return 1;
288 }
289
290 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000291 if (id1 == flash->manufacture_id &&
Peter Stugeda4e5f32008-06-24 01:22:03 +0000292 GENERIC_DEVICE_ID == flash->model_id)
293 return 1;
294
Carl-Daniel Hailfinger01d49ed2009-11-20 01:12:45 +0000295 /* Test if there is any vendor ID. */
296 if (GENERIC_MANUF_ID == flash->manufacture_id &&
297 id1 != 0xff)
298 return 1;
299
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000300 return 0;
301}
302
Uwe Hermann394131e2008-10-18 21:14:13 +0000303int probe_spi_rdid(struct flashchip *flash)
304{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000305 return probe_spi_rdid_generic(flash, 3);
306}
307
308/* support 4 bytes flash ID */
Uwe Hermann394131e2008-10-18 21:14:13 +0000309int probe_spi_rdid4(struct flashchip *flash)
310{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000311 /* only some SPI chipsets support 4 bytes commands */
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000312 switch (spi_controller) {
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +0000313#if INTERNAL_SUPPORT == 1
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000314 case SPI_CONTROLLER_ICH7:
315 case SPI_CONTROLLER_ICH9:
316 case SPI_CONTROLLER_VIA:
317 case SPI_CONTROLLER_SB600:
318 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +0000319#endif
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000320#if FT2232_SPI_SUPPORT == 1
Paul Fox05dfbe62009-06-16 21:08:06 +0000321 case SPI_CONTROLLER_FT2232:
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000322#endif
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000323#if DUMMY_SUPPORT == 1
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000324 case SPI_CONTROLLER_DUMMY:
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000325#endif
Carl-Daniel Hailfingerd5b28fa2009-11-24 18:27:10 +0000326#if BUSPIRATE_SPI_SUPPORT == 1
327 case SPI_CONTROLLER_BUSPIRATE:
328#endif
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000329 return probe_spi_rdid_generic(flash, 4);
330 default:
331 printf_debug("4b ID not supported on this SPI controller\n");
332 }
333
334 return 0;
Rudolf Marek48a85e42008-06-30 21:45:17 +0000335}
336
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000337int probe_spi_rems(struct flashchip *flash)
338{
339 unsigned char readarr[JEDEC_REMS_INSIZE];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000340 uint32_t id1, id2;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000341
342 if (spi_rems(readarr))
343 return 0;
344
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000345 id1 = readarr[0];
346 id2 = readarr[1];
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000347
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000348 printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000349
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000350 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000351 /* Print the status register to tell the
352 * user about possible write protection.
353 */
354 spi_prettyprint_status_register(flash);
355
356 return 1;
357 }
358
359 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000360 if (id1 == flash->manufacture_id &&
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000361 GENERIC_DEVICE_ID == flash->model_id)
362 return 1;
363
Carl-Daniel Hailfinger01d49ed2009-11-20 01:12:45 +0000364 /* Test if there is any vendor ID. */
365 if (GENERIC_MANUF_ID == flash->manufacture_id &&
366 id1 != 0xff)
367 return 1;
368
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000369 return 0;
370}
371
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000372int probe_spi_res(struct flashchip *flash)
373{
374 unsigned char readarr[3];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000375 uint32_t id2;
Peter Stugeda4e5f32008-06-24 01:22:03 +0000376
Carl-Daniel Hailfinger92a54ca2008-11-27 22:48:48 +0000377 /* Check if RDID was successful and did not return 0xff 0xff 0xff.
378 * In that case, RES is pointless.
379 */
380 if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) ||
381 (readarr[1] != 0xff) || (readarr[2] != 0xff)))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000382 return 0;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000383
Peter Stugeda4e5f32008-06-24 01:22:03 +0000384 if (spi_res(readarr))
385 return 0;
386
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000387 id2 = readarr[0];
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000388 printf_debug("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000389 if (id2 != flash->model_id)
Peter Stugeda4e5f32008-06-24 01:22:03 +0000390 return 0;
391
392 /* Print the status register to tell the
393 * user about possible write protection.
394 */
395 spi_prettyprint_status_register(flash);
396 return 1;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000397}
398
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000399uint8_t spi_read_status_register(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000400{
Uwe Hermann394131e2008-10-18 21:14:13 +0000401 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000402 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
Peter Stugebf196e92009-01-26 03:08:45 +0000403 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000404 int ret;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000405
406 /* Read Status Register */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000407 ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
408 if (ret)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000409 fprintf(stderr, "RDSR failed!\n");
Jason Wanga3f04be2008-11-28 21:36:51 +0000410
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000411 return readarr[0];
412}
413
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000414/* Prettyprint the status register. Common definitions. */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000415void spi_prettyprint_status_register_common(uint8_t status)
416{
417 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000418 "%sset\n", (status & (1 << 5)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000419 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000420 "%sset\n", (status & (1 << 4)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000421 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000422 "%sset\n", (status & (1 << 3)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000423 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000424 "%sset\n", (status & (1 << 2)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000425 printf_debug("Chip status register: Write Enable Latch (WEL) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000426 "%sset\n", (status & (1 << 1)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000427 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000428 "%sset\n", (status & (1 << 0)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000429}
430
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000431/* Prettyprint the status register. Works for
432 * ST M25P series
433 * MX MX25L series
434 */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000435void spi_prettyprint_status_register_st_m25p(uint8_t status)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000436{
437 printf_debug("Chip status register: Status Register Write Disable "
Uwe Hermann394131e2008-10-18 21:14:13 +0000438 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000439 printf_debug("Chip status register: Bit 6 is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000440 "%sset\n", (status & (1 << 6)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000441 spi_prettyprint_status_register_common(status);
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000442}
443
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000444void spi_prettyprint_status_register_sst25(uint8_t status)
445{
446 printf_debug("Chip status register: Block Protect Write Disable "
447 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
448 printf_debug("Chip status register: Auto Address Increment Programming "
449 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
450 spi_prettyprint_status_register_common(status);
451}
452
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000453/* Prettyprint the status register. Works for
454 * SST 25VF016
455 */
456void spi_prettyprint_status_register_sst25vf016(uint8_t status)
457{
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000458 const char *bpt[] = {
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000459 "none",
460 "1F0000H-1FFFFFH",
461 "1E0000H-1FFFFFH",
462 "1C0000H-1FFFFFH",
463 "180000H-1FFFFFH",
464 "100000H-1FFFFFH",
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000465 "all", "all"
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000466 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000467 spi_prettyprint_status_register_sst25(status);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000468 printf_debug("Resulting block protection : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000469 bpt[(status & 0x1c) >> 2]);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000470}
471
Peter Stuge5fecee42009-01-26 03:23:50 +0000472void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
473{
474 const char *bpt[] = {
475 "none",
476 "0x70000-0x7ffff",
477 "0x60000-0x7ffff",
478 "0x40000-0x7ffff",
479 "all blocks", "all blocks", "all blocks", "all blocks"
480 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000481 spi_prettyprint_status_register_sst25(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000482 printf_debug("Resulting block protection : %s\n",
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000483 bpt[(status & 0x1c) >> 2]);
Peter Stuge5fecee42009-01-26 03:23:50 +0000484}
485
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000486void spi_prettyprint_status_register(struct flashchip *flash)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000487{
488 uint8_t status;
489
Peter Stugefa8c5502008-05-10 23:07:52 +0000490 status = spi_read_status_register();
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000491 printf_debug("Chip status register is %02x\n", status);
492 switch (flash->manufacture_id) {
493 case ST_ID:
Carl-Daniel Hailfingerf43e6422008-05-15 22:32:08 +0000494 if (((flash->model_id & 0xff00) == 0x2000) ||
495 ((flash->model_id & 0xff00) == 0x2500))
496 spi_prettyprint_status_register_st_m25p(status);
497 break;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000498 case MX_ID:
499 if ((flash->model_id & 0xff00) == 0x2000)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000500 spi_prettyprint_status_register_st_m25p(status);
501 break;
502 case SST_ID:
Peter Stuge5fecee42009-01-26 03:23:50 +0000503 switch (flash->model_id) {
504 case 0x2541:
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000505 spi_prettyprint_status_register_sst25vf016(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000506 break;
507 case 0x8d:
508 case 0x258d:
509 spi_prettyprint_status_register_sst25vf040b(status);
510 break;
Carl-Daniel Hailfinger5100a8a2009-05-13 22:51:27 +0000511 default:
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000512 spi_prettyprint_status_register_sst25(status);
513 break;
Peter Stuge5fecee42009-01-26 03:23:50 +0000514 }
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000515 break;
516 }
517}
Uwe Hermann394131e2008-10-18 21:14:13 +0000518
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000519int spi_chip_erase_60(struct flashchip *flash)
520{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000521 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000522 struct spi_command cmds[] = {
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000523 {
524 .writecnt = JEDEC_WREN_OUTSIZE,
525 .writearr = (const unsigned char[]){ JEDEC_WREN },
526 .readcnt = 0,
527 .readarr = NULL,
528 }, {
529 .writecnt = JEDEC_CE_60_OUTSIZE,
530 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
531 .readcnt = 0,
532 .readarr = NULL,
533 }, {
534 .writecnt = 0,
535 .writearr = NULL,
536 .readcnt = 0,
537 .readarr = NULL,
538 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000539
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000540 result = spi_disable_blockprotect();
541 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000542 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000543 return result;
544 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000545
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000546 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000547 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000548 fprintf(stderr, "%s failed during command execution\n",
549 __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000550 return result;
551 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000552 /* Wait until the Write-In-Progress bit is cleared.
553 * This usually takes 1-85 s, so wait in 1 s steps.
554 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000555 /* FIXME: We assume spi_read_status_register will never fail. */
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000556 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000557 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000558 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
559 fprintf(stderr, "ERASE FAILED!\n");
560 return -1;
561 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000562 return 0;
563}
564
Peter Stugefa8c5502008-05-10 23:07:52 +0000565int spi_chip_erase_c7(struct flashchip *flash)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000566{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000567 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000568 struct spi_command cmds[] = {
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000569 {
570 .writecnt = JEDEC_WREN_OUTSIZE,
571 .writearr = (const unsigned char[]){ JEDEC_WREN },
572 .readcnt = 0,
573 .readarr = NULL,
574 }, {
575 .writecnt = JEDEC_CE_C7_OUTSIZE,
576 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
577 .readcnt = 0,
578 .readarr = NULL,
579 }, {
580 .writecnt = 0,
581 .writearr = NULL,
582 .readcnt = 0,
583 .readarr = NULL,
584 }};
Uwe Hermann394131e2008-10-18 21:14:13 +0000585
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000586 result = spi_disable_blockprotect();
587 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000588 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000589 return result;
590 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000591
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000592 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000593 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000594 fprintf(stderr, "%s failed during command execution\n", __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000595 return result;
596 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000597 /* Wait until the Write-In-Progress bit is cleared.
598 * This usually takes 1-85 s, so wait in 1 s steps.
599 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000600 /* FIXME: We assume spi_read_status_register will never fail. */
Peter Stugefa8c5502008-05-10 23:07:52 +0000601 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000602 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000603 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
604 fprintf(stderr, "ERASE FAILED!\n");
605 return -1;
606 }
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000607 return 0;
608}
609
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000610int spi_chip_erase_60_c7(struct flashchip *flash)
611{
612 int result;
613 result = spi_chip_erase_60(flash);
614 if (result) {
615 printf_debug("spi_chip_erase_60 failed, trying c7\n");
616 result = spi_chip_erase_c7(flash);
617 }
618 return result;
619}
620
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000621int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000622{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000623 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000624 struct spi_command cmds[] = {
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000625 {
626 .writecnt = JEDEC_WREN_OUTSIZE,
627 .writearr = (const unsigned char[]){ JEDEC_WREN },
628 .readcnt = 0,
629 .readarr = NULL,
630 }, {
631 .writecnt = JEDEC_BE_52_OUTSIZE,
632 .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
633 .readcnt = 0,
634 .readarr = NULL,
635 }, {
636 .writecnt = 0,
637 .writearr = NULL,
638 .readcnt = 0,
639 .readarr = NULL,
640 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000641
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000642 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000643 if (result) {
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000644 fprintf(stderr, "%s failed during command execution at address 0x%x\n",
645 __func__, addr);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000646 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000647 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000648 /* Wait until the Write-In-Progress bit is cleared.
649 * This usually takes 100-4000 ms, so wait in 100 ms steps.
650 */
651 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000652 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000653 if (check_erased_range(flash, addr, blocklen)) {
654 fprintf(stderr, "ERASE FAILED!\n");
655 return -1;
656 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000657 return 0;
658}
659
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000660/* Block size is usually
661 * 64k for Macronix
662 * 32k for SST
663 * 4-32k non-uniform for EON
664 */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000665int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000666{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000667 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000668 struct spi_command cmds[] = {
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000669 {
670 .writecnt = JEDEC_WREN_OUTSIZE,
671 .writearr = (const unsigned char[]){ JEDEC_WREN },
672 .readcnt = 0,
673 .readarr = NULL,
674 }, {
675 .writecnt = JEDEC_BE_D8_OUTSIZE,
676 .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
677 .readcnt = 0,
678 .readarr = NULL,
679 }, {
680 .writecnt = 0,
681 .writearr = NULL,
682 .readcnt = 0,
683 .readarr = NULL,
684 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000685
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000686 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000687 if (result) {
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000688 fprintf(stderr, "%s failed during command execution at address 0x%x\n",
689 __func__, addr);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000690 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000691 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000692 /* Wait until the Write-In-Progress bit is cleared.
693 * This usually takes 100-4000 ms, so wait in 100 ms steps.
694 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000695 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000696 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000697 if (check_erased_range(flash, addr, blocklen)) {
698 fprintf(stderr, "ERASE FAILED!\n");
699 return -1;
700 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000701 return 0;
702}
703
Stefan Reinauer424ed222008-10-29 22:13:20 +0000704int spi_chip_erase_d8(struct flashchip *flash)
705{
706 int i, rc = 0;
707 int total_size = flash->total_size * 1024;
708 int erase_size = 64 * 1024;
709
710 spi_disable_blockprotect();
711
712 printf("Erasing chip: \n");
713
714 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000715 rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000716 if (rc) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000717 fprintf(stderr, "Error erasing block at 0x%x\n", i);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000718 break;
719 }
720 }
721
722 printf("\n");
723
724 return rc;
725}
726
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000727/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000728int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000729{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000730 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000731 struct spi_command cmds[] = {
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000732 {
733 .writecnt = JEDEC_WREN_OUTSIZE,
734 .writearr = (const unsigned char[]){ JEDEC_WREN },
735 .readcnt = 0,
736 .readarr = NULL,
737 }, {
738 .writecnt = JEDEC_SE_OUTSIZE,
739 .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
740 .readcnt = 0,
741 .readarr = NULL,
742 }, {
743 .writecnt = 0,
744 .writearr = NULL,
745 .readcnt = 0,
746 .readarr = NULL,
747 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000748
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000749 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000750 if (result) {
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000751 fprintf(stderr, "%s failed during command execution at address 0x%x\n",
752 __func__, addr);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000753 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000754 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000755 /* Wait until the Write-In-Progress bit is cleared.
756 * This usually takes 15-800 ms, so wait in 10 ms steps.
757 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000758 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000759 programmer_delay(10 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000760 if (check_erased_range(flash, addr, blocklen)) {
761 fprintf(stderr, "ERASE FAILED!\n");
762 return -1;
763 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000764 return 0;
765}
766
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000767int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
768{
769 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000770 fprintf(stderr, "%s called with incorrect arguments\n",
771 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000772 return -1;
773 }
774 return spi_chip_erase_60(flash);
775}
776
777int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
778{
779 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000780 fprintf(stderr, "%s called with incorrect arguments\n",
781 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000782 return -1;
783 }
784 return spi_chip_erase_c7(flash);
785}
786
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000787int spi_write_status_enable(void)
Jason Wanga3f04be2008-11-28 21:36:51 +0000788{
789 const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000790 int result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000791
792 /* Send EWSR (Enable Write Status Register). */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000793 result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000794
795 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000796 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000797
798 return result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000799}
800
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000801/*
802 * This is according the SST25VF016 datasheet, who knows it is more
803 * generic that this...
804 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000805int spi_write_status_register(int status)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000806{
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000807 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000808 struct spi_command cmds[] = {
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000809 {
810 .writecnt = JEDEC_EWSR_OUTSIZE,
811 .writearr = (const unsigned char[]){ JEDEC_EWSR },
812 .readcnt = 0,
813 .readarr = NULL,
814 }, {
815 .writecnt = JEDEC_WRSR_OUTSIZE,
816 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
817 .readcnt = 0,
818 .readarr = NULL,
819 }, {
820 .writecnt = 0,
821 .writearr = NULL,
822 .readcnt = 0,
823 .readarr = NULL,
824 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000825
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000826 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000827 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000828 fprintf(stderr, "%s failed during command execution\n",
829 __func__);
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000830 }
831 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000832}
833
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000834int spi_byte_program(int addr, uint8_t byte)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000835{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000836 int result;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000837 struct spi_command cmds[] = {
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000838 {
839 .writecnt = JEDEC_WREN_OUTSIZE,
840 .writearr = (const unsigned char[]){ JEDEC_WREN },
841 .readcnt = 0,
842 .readarr = NULL,
843 }, {
844 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
845 .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte },
846 .readcnt = 0,
847 .readarr = NULL,
848 }, {
849 .writecnt = 0,
850 .writearr = NULL,
851 .readcnt = 0,
852 .readarr = NULL,
853 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000854
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000855 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000856 if (result) {
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000857 fprintf(stderr, "%s failed during command execution at address 0x%x\n",
858 __func__, addr);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000859 }
860 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000861}
862
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000863int spi_nbyte_program(int addr, uint8_t *bytes, int len)
Paul Foxeb3acef2009-06-12 08:10:33 +0000864{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000865 int result;
866 /* FIXME: Switch to malloc based on len unless that kills speed. */
Paul Foxeb3acef2009-06-12 08:10:33 +0000867 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
868 JEDEC_BYTE_PROGRAM,
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000869 (addr >> 16) & 0xff,
870 (addr >> 8) & 0xff,
871 (addr >> 0) & 0xff,
Paul Foxeb3acef2009-06-12 08:10:33 +0000872 };
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000873 struct spi_command cmds[] = {
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000874 {
875 .writecnt = JEDEC_WREN_OUTSIZE,
876 .writearr = (const unsigned char[]){ JEDEC_WREN },
877 .readcnt = 0,
878 .readarr = NULL,
879 }, {
880 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
881 .writearr = cmd,
882 .readcnt = 0,
883 .readarr = NULL,
884 }, {
885 .writecnt = 0,
886 .writearr = NULL,
887 .readcnt = 0,
888 .readarr = NULL,
889 }};
Paul Foxeb3acef2009-06-12 08:10:33 +0000890
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000891 if (!len) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000892 fprintf(stderr, "%s called for zero-length write\n", __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000893 return 1;
894 }
Paul Foxeb3acef2009-06-12 08:10:33 +0000895 if (len > 256) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000896 fprintf(stderr, "%s called for too long a write\n", __func__);
Paul Foxeb3acef2009-06-12 08:10:33 +0000897 return 1;
898 }
899
900 memcpy(&cmd[4], bytes, len);
901
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000902 result = spi_send_multicommand(cmds);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000903 if (result) {
Carl-Daniel Hailfinger3efc51c2009-11-16 15:03:35 +0000904 fprintf(stderr, "%s failed during command execution at address 0x%x\n",
905 __func__, addr);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000906 }
907 return result;
Paul Foxeb3acef2009-06-12 08:10:33 +0000908}
909
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000910int spi_disable_blockprotect(void)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000911{
912 uint8_t status;
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000913 int result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000914
Peter Stugefa8c5502008-05-10 23:07:52 +0000915 status = spi_read_status_register();
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000916 /* If there is block protection in effect, unprotect it first. */
917 if ((status & 0x3c) != 0) {
918 printf_debug("Some block protection in effect, disabling\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000919 result = spi_write_status_register(status & ~0x3c);
920 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000921 fprintf(stderr, "spi_write_status_register failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000922 return result;
923 }
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000924 }
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000925 return 0;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000926}
927
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000928int spi_nbyte_read(int address, uint8_t *bytes, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000929{
Uwe Hermann394131e2008-10-18 21:14:13 +0000930 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
931 JEDEC_READ,
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000932 (address >> 16) & 0xff,
933 (address >> 8) & 0xff,
934 (address >> 0) & 0xff,
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000935 };
936
937 /* Send Read */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000938 return spi_send_command(sizeof(cmd), len, cmd, bytes);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000939}
940
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000941/*
942 * Read a complete flash chip.
943 * Each page is read separately in chunks with a maximum size of chunksize.
944 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000945int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000946{
947 int rc = 0;
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000948 int i, j, starthere, lenhere;
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000949 int page_size = flash->page_size;
950 int toread;
951
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000952 /* Warning: This loop has a very unusual condition and body.
953 * The loop needs to go through each page with at least one affected
954 * byte. The lowest page number is (start / page_size) since that
955 * division rounds down. The highest page number we want is the page
956 * where the last byte of the range lives. That last byte has the
957 * address (start + len - 1), thus the highest page number is
958 * (start + len - 1) / page_size. Since we want to include that last
959 * page as well, the loop condition uses <=.
960 */
961 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
962 /* Byte position of the first byte in the range in this page. */
963 /* starthere is an offset to the base address of the chip. */
964 starthere = max(start, i * page_size);
965 /* Length of bytes in the range in this page. */
966 lenhere = min(start + len, (i + 1) * page_size) - starthere;
967 for (j = 0; j < lenhere; j += chunksize) {
968 toread = min(chunksize, lenhere - j);
969 rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000970 if (rc)
971 break;
972 }
973 if (rc)
974 break;
975 }
976
977 return rc;
978}
979
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000980int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000981{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000982 if (!spi_programmer[spi_controller].read) {
983 fprintf(stderr, "%s called, but SPI read is unsupported on this"
984 " hardware. Please report a bug.\n", __func__);
985 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000986 }
987
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000988 return spi_programmer[spi_controller].read(flash, buf, start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000989}
990
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000991/*
992 * Program chip using byte programming. (SLOW!)
993 * This is for chips which can only handle one byte writes
994 * and for chips where memory mapped programming is impossible
995 * (e.g. due to size constraints in IT87* for over 512 kB)
996 */
997int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
998{
999 int total_size = 1024 * flash->total_size;
Carl-Daniel Hailfingerde75a5e2009-10-01 13:16:32 +00001000 int i, result = 0;
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001001
1002 spi_disable_blockprotect();
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +00001003 /* Erase first */
1004 printf("Erasing flash before programming... ");
Carl-Daniel Hailfingerf38431a2009-09-05 02:30:58 +00001005 if (erase_flash(flash)) {
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +00001006 fprintf(stderr, "ERASE FAILED!\n");
1007 return -1;
1008 }
1009 printf("done.\n");
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001010 for (i = 0; i < total_size; i++) {
Carl-Daniel Hailfingerde75a5e2009-10-01 13:16:32 +00001011 result = spi_byte_program(i, buf[i]);
1012 if (result)
1013 return 1;
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001014 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001015 programmer_delay(10);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001016 }
1017
1018 return 0;
1019}
1020
1021/*
1022 * Program chip using page (256 bytes) programming.
1023 * Some SPI masters can't do this, they use single byte programming instead.
1024 */
Carl-Daniel Hailfinger8d497012009-05-09 02:34:18 +00001025int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001026{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001027 if (!spi_programmer[spi_controller].write_256) {
1028 fprintf(stderr, "%s called, but SPI page write is unsupported "
1029 " on this hardware. Please report a bug.\n", __func__);
1030 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001031 }
1032
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001033 return spi_programmer[spi_controller].write_256(flash, buf);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +00001034}
Peter Stugefd9217d2009-01-26 03:37:40 +00001035
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +00001036uint32_t spi_get_valid_read_addr(void)
1037{
1038 /* Need to return BBAR for ICH chipsets. */
1039 return 0;
1040}
1041
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001042int spi_aai_write(struct flashchip *flash, uint8_t *buf)
1043{
Peter Stugefd9217d2009-01-26 03:37:40 +00001044 uint32_t pos = 2, size = flash->total_size * 1024;
1045 unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001046 int result;
1047
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +00001048 switch (spi_controller) {
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +00001049#if INTERNAL_SUPPORT == 1
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +00001050 case SPI_CONTROLLER_WBSIO:
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001051 fprintf(stderr, "%s: impossible with Winbond SPI masters,"
1052 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001053 return spi_chip_write_1(flash, buf);
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +00001054#endif
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001055 default:
1056 break;
Peter Stugefd9217d2009-01-26 03:37:40 +00001057 }
Carl-Daniel Hailfingerf38431a2009-09-05 02:30:58 +00001058 if (erase_flash(flash)) {
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00001059 fprintf(stderr, "ERASE FAILED!\n");
1060 return -1;
1061 }
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001062 result = spi_write_enable();
1063 if (result)
1064 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001065 spi_send_command(6, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001066 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001067 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001068 while (pos < size) {
1069 w[1] = buf[pos++];
1070 w[2] = buf[pos++];
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001071 spi_send_command(3, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001072 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001073 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001074 }
1075 spi_write_disable();
1076 return 0;
1077}