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review.sourcearcade.org / flashprog / d42f1f65b023a4845feb1f7022eb8f2081a39b3d / . / gfxnvidia.c
blob: e353684aa8277bf7e768e943bb941303e40603d8 [file] [log] [blame]
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]15 */
16
17#include <stdlib.h>
18#include <string.h>
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]19#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000[diff] [blame]20#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +0000[diff] [blame]21#include "hwaccess.h"
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]22
23#define PCI_VENDOR_ID_NVIDIA 0x10de
24
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +0000[diff] [blame]25/* Mask to restrict flash accesses to a 128kB memory window.
26 * FIXME: Is this size a one-fits-all or card dependent?
27 */
28#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
David Hendricks8bb20212011-06-14 01:35:36 +0000[diff] [blame]29#define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +0000[diff] [blame]30
Jacob Garberafc3ad62019-06-24 16:05:28 -0600[diff] [blame]31static uint8_t *nvidia_bar;
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]32
Thomas Heijligencc853d82021-05-04 15:32:17 +0200[diff] [blame]33static const struct dev_entry gfx_nvidia[] = {
Michael Karcher84486392010-02-24 00:04:40 +0000[diff] [blame]34 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
35 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
36 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
37 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
38 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
39 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
40 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
41 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
42 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
43 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
44 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
45 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
46 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
47 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
48 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
49 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
50 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
51 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
52 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
53 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
54 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
55 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
56 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]57
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000[diff] [blame]58 {0},
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]59};
60
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000[diff] [blame]61static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
62 chipaddr addr);
63static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
64 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000[diff] [blame]65static const struct par_master par_master_gfxnvidia = {
Felix Singerdd547c72021-10-13 13:56:38 +0200[diff] [blame]66 .chip_readb = gfxnvidia_chip_readb,
67 .chip_readw = fallback_chip_readw,
68 .chip_readl = fallback_chip_readl,
69 .chip_readn = fallback_chip_readn,
70 .chip_writeb = gfxnvidia_chip_writeb,
71 .chip_writew = fallback_chip_writew,
72 .chip_writel = fallback_chip_writel,
73 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000[diff] [blame]74};
75
Thomas Heijligencc853d82021-05-04 15:32:17 +0200[diff] [blame]76static int gfxnvidia_init(void)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]77{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000[diff] [blame]78 struct pci_dev *dev = NULL;
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]79 uint32_t reg32;
80
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000[diff] [blame]81 if (rget_io_perms())
82 return 1;
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]83
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000[diff] [blame]84 dev = pcidev_init(gfx_nvidia, PCI_BASE_ADDRESS_0);
85 if (!dev)
86 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000[diff] [blame]87
Stefan Tauner0ccec8f2014-06-01 23:49:03 +0000[diff] [blame]88 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000[diff] [blame]89 if (!io_base_addr)
90 return 1;
91
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]92 io_base_addr += 0x300000;
Sean Nelson8e5e73e2010-01-09 23:54:05 +0000[diff] [blame]93 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]94
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000[diff] [blame]95 nvidia_bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
96 if (nvidia_bar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +0000[diff] [blame]97 return 1;
98
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]99 /* Allow access to flash interface (will disable screen). */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000[diff] [blame]100 reg32 = pci_read_long(dev, 0x50);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]101 reg32 &= ~(1 << 0);
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000[diff] [blame]102 rpci_write_long(dev, 0x50, reg32);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]103
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000[diff] [blame]104 /* Write/erase doesn't work. */
105 programmer_may_write = 0;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000[diff] [blame]106 register_par_master(&par_master_gfxnvidia, BUS_PARALLEL);
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000[diff] [blame]107
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]108 return 0;
109}
110
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000[diff] [blame]111static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
112 chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]113{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000[diff] [blame]114 pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]115}
116
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000[diff] [blame]117static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
118 const chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]119{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000[diff] [blame]120 return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000[diff] [blame]121}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200[diff] [blame]122
123const struct programmer_entry programmer_gfxnvidia = {
124 .name = "gfxnvidia",
125 .type = PCI,
126 .devs.dev = gfx_nvidia,
127 .init = gfxnvidia_init,
128 .map_flash_region = fallback_map,
129 .unmap_flash_region = fallback_unmap,
130 .delay = internal_delay,
131};