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Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2011 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000014 */
15
16/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
17
18#include <stdlib.h>
19#include "flash.h"
20#include "programmer.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010021#include "hwaccess_physmap.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010022#include "platform/pci.h"
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000023
Jacob Garberafc3ad62019-06-24 16:05:28 -060024static uint8_t *nicintel_bar;
25static uint8_t *nicintel_control_bar;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000026
Thomas Heijligencc853d82021-05-04 15:32:17 +020027static const struct dev_entry nics_intel[] = {
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000028 {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +000029 {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000030
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000031 {0},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000032};
33
34/* Arbitrary limit, taken from the datasheet I just had lying around.
35 * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
36 */
37#define NICINTEL_MEMMAP_SIZE (128 * 1024)
38#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
39
Elyes HAOUAS124ef382018-03-27 12:15:09 +020040#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
David Hendricks8bb20212011-06-14 01:35:36 +000041
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000042#define CSR_FCR 0x0c
43
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000044static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
45 chipaddr addr);
46static uint8_t nicintel_chip_readb(const struct flashctx *flash,
47 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000048static const struct par_master par_master_nicintel = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020049 .chip_readb = nicintel_chip_readb,
50 .chip_readw = fallback_chip_readw,
51 .chip_readl = fallback_chip_readl,
52 .chip_readn = fallback_chip_readn,
53 .chip_writeb = nicintel_chip_writeb,
54 .chip_writew = fallback_chip_writew,
55 .chip_writel = fallback_chip_writel,
56 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000057};
58
Thomas Heijligencc853d82021-05-04 15:32:17 +020059static int nicintel_init(void)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000060{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000061 struct pci_dev *dev = NULL;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000062 uintptr_t addr;
63
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000064 /* FIXME: BAR2 is not available if the device uses the CardBus function. */
65 dev = pcidev_init(nics_intel, PCI_BASE_ADDRESS_2);
66 if (!dev)
67 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000068
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000069 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
Niklas Söderlund89edf362013-08-23 23:29:23 +000070 if (!addr)
71 return 1;
72
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000073 nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000074 if (nicintel_bar == ERROR_PTR)
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000075 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000076
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000077 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000078 if (!addr)
79 return 1;
80
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000081 nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000082 if (nicintel_control_bar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +000083 return 1;
84
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000085 /* FIXME: This register is pretty undocumented in all publicly available
86 * documentation from Intel. Let me quote the complete info we have:
87 * "Flash Control Register: The Flash Control register allows the CPU to
88 * enable writes to an external Flash. The Flash Control Register is a
89 * 32-bit field that allows access to an external Flash device."
90 * Ah yes, we also know where it is, but we have absolutely _no_ idea
91 * what we should do with it. Write 0x0001 because we have nothing
92 * better to do with our time.
93 */
94 pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
95
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000096 max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +100097 return register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000098}
99
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000100static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
101 chipaddr addr)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000102{
103 pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
104}
105
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000106static uint8_t nicintel_chip_readb(const struct flashctx *flash,
107 const chipaddr addr)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000108{
109 return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
110}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200111
112const struct programmer_entry programmer_nicintel = {
113 .name = "nicintel",
114 .type = PCI,
115 .devs.dev = nics_intel,
116 .init = nicintel_init,
Thomas Heijligencc853d82021-05-04 15:32:17 +0200117};