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Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010,2011 Carl-Daniel Hailfinger
5 * Written by Carl-Daniel Hailfinger for Angelbird Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/* Datasheets are not public (yet?) */
22
23#include <stdlib.h>
24#include "flash.h"
25#include "programmer.h"
26
27uint8_t *mv_bar;
28uint16_t mv_iobar;
29
30const struct pcidev_status satas_mv[] = {
31 /* 88SX6041 and 88SX6042 are the same according to the datasheet. */
32 {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
33
34 {},
35};
36
37#define NVRAM_PARAM 0x1045c
38#define FLASH_PARAM 0x1046c
39#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
40#define PCI_BAR2_CONTROL 0x00c08
41#define GPIO_PORT_CONTROL 0x104f0
42
43/*
44 * Random notes:
45 * FCE# Flash Chip Enable
46 * FWE# Flash Write Enable
47 * FOE# Flash Output Enable
48 * FALE[1:0] Flash Address Latch Enable
49 * FAD[7:0] Flash Multiplexed Address/Data Bus
50 * FA[2:0] Flash Address Low
51 *
52 * GPIO[15,2] GPIO Port Mode
53 * GPIO[4:3] Flash Size
54 *
55 * 0xd2c Expansion ROM BAR Control
56 * 0xc08 PCI BAR2 (Flash/NVRAM) Control
57 * 0x1046c Flash Parameters
58 */
59int satamv_init(void)
60{
61 uintptr_t addr;
62 uint32_t tmp;
63
64 get_io_perms();
65
66 /* BAR0 has all internal registers memory mapped. */
67 /* No need to check for errors, pcidev_init() will not return in case
68 * of errors.
69 */
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000070 addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000071
72 mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000);
73 if (mv_bar == ERROR_PTR)
74 goto error_out;
75
76 tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
77 msg_pspew("Flash Parameters:\n");
78 msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
79 msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
80 msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
81 msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
82 msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
83 msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
84 msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
85 msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
86 msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
87 msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
88 msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
89 msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
90 msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
91 msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
92
93 tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
94 msg_pspew("Expansion ROM BAR Control:\n");
95 msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
96
97 /* Enable BAR2 mapping to flash */
98 tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
99 msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
100 msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
101 msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
102 msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
103 tmp &= 0xffffffc0;
104 tmp |= 0x0000001f;
105 /* FIXME: This needs to be an auto-reversible write. */
106 pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
107
108 /* Enable flash: GPIO Port Control Register 0x104f0 */
109 tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
110 msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
111 if (((tmp >> 0) & 0x3) != 0x2)
112 msg_pinfo("Warning! Either the straps are incorrect or you "
113 "have no flash or someone overwrote the strap "
114 "values!\n");
115 tmp &= 0xfffffffc;
116 tmp |= 0x2;
117 /* FIXME: This needs to be an auto-reversible write. */
118 pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
119
120 /* Get I/O BAR location. */
121 tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &
122 PCI_BASE_ADDRESS_IO_MASK;
123 /* Truncate to reachable range.
124 * FIXME: Check if the I/O BAR is actually reachable.
125 * This is an arch specific check.
126 */
127 mv_iobar = tmp & 0xffff;
128 msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
129
130 buses_supported = CHIP_BUSTYPE_PARALLEL;
131
132 /* 512 kByte with two 8-bit latches, and
133 * 4 MByte with additional 3-bit latch. */
134 max_rom_decode.parallel = 4 * 1024 * 1024;
135
136 return 0;
137
138error_out:
139 pci_cleanup(pacc);
140 release_io_perms();
141 return 1;
142}
143
144int satamv_shutdown(void)
145{
146 physunmap(mv_bar, 0x20000);
147 pci_cleanup(pacc);
148 release_io_perms();
149 return 0;
150}
151
152/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
153 * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
154 * This code only supports indirect accesses for now.
155 */
156
157/* Indirect access to via the I/O BAR1. */
158static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
159{
160 /* 0x80000000 selects BAR2 for remapping. */
161 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
162 OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
163}
164
165/* Indirect access to via the I/O BAR1. */
166static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
167{
168 /* 0x80000000 selects BAR2 for remapping. */
169 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
170 return INB(mv_iobar + 0x80 + (addr & 0x3));
171}
172
173/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
174void satamv_chip_writeb(uint8_t val, chipaddr addr)
175{
176 satamv_indirect_chip_writeb(val, addr);
177}
178
179/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
180uint8_t satamv_chip_readb(const chipaddr addr)
181{
182 return satamv_indirect_chip_readb(addr);
183}