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Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Tauner1e146392011-09-15 23:52:55 +000016 */
17
Stefan Tauner1e146392011-09-15 23:52:55 +000018#ifndef __ICH_DESCRIPTORS_H__
19#define __ICH_DESCRIPTORS_H__ 1
20
Nico Huber4d440a72017-08-15 11:26:48 +020021#include <sys/types.h>
Stefan Tauner1e146392011-09-15 23:52:55 +000022#include <stdint.h>
Stefan Taunera8d838d2011-11-06 23:51:09 +000023#include "programmer.h" /* for enum ich_chipset */
Stefan Tauner1e146392011-09-15 23:52:55 +000024
25/* FIXME: Replace with generic return codes */
26#define ICH_RET_OK 0
27#define ICH_RET_ERR -1
28#define ICH_RET_WARN -2
29#define ICH_RET_PARAM -3
30#define ICH_RET_OOB -4
31
32#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */
Nico Huberd54e4f42017-03-23 23:45:47 +010033#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000034 /* 0-1: reserved */
35#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */
36#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF)
37#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */
38#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF)
39 /* 15-31: reserved */
40
41#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */
Nico Huberd54e4f42017-03-23 23:45:47 +010042#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000043
44/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
45 * descriptor are equal therefore they all share the same macros below. */
46#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */
47#define VSCC_BES (0x3 << VSCC_BES_OFF)
48#define VSCC_WG_OFF 2 /* 2: Write Granularity */
49#define VSCC_WG (0x1 << VSCC_WG_OFF)
50#define VSCC_WSR_OFF 3 /* 3: Write Status Required */
51#define VSCC_WSR (0x1 << VSCC_WSR_OFF)
52#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */
53#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF)
54 /* 5-7: reserved */
55#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */
56#define VSCC_EO (0xff << VSCC_EO_OFF)
57 /* 16-22: reserved */
58#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */
59#define VSCC_VCL (0x1 << VSCC_VCL_OFF)
60 /* 24-31: reserved */
61
Nico Huberfa622942017-03-24 17:25:37 +010062#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x07fff000)
63#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x07fff000) | 0x00000fff)
Stefan Tauner1e146392011-09-15 23:52:55 +000064
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000065void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl);
Stefan Tauner1e146392011-09-15 23:52:55 +000066
67struct ich_desc_content {
68 uint32_t FLVALSIG; /* 0x00 */
69 union { /* 0x04 */
70 uint32_t FLMAP0;
71 struct {
72 uint32_t FCBA :8, /* Flash Component Base Address */
73 NC :2, /* Number Of Components */
74 :6,
75 FRBA :8, /* Flash Region Base Address */
Nico Huberfa622942017-03-24 17:25:37 +010076 NR :3, /* Number Of Regions (reserved from Skylake on) */
Stefan Tauner1e146392011-09-15 23:52:55 +000077 :5;
78 };
79 };
80 union { /* 0x08 */
81 uint32_t FLMAP1;
82 struct {
83 uint32_t FMBA :8, /* Flash Master Base Address */
84 NM :3, /* Number Of Masters */
85 :5,
86 FISBA :8, /* Flash ICH Strap Base Address */
87 ISL :8; /* ICH Strap Length */
88 };
89 };
90 union { /* 0x0c */
91 uint32_t FLMAP2;
92 struct {
Nico Huber1dc3d422017-06-17 00:09:31 +020093 uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
94 MSL :8, /* MCH Strap Length */
95 ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */
96 RIL :8; /* Register Init Length (new since Hawell) */
Stefan Tauner1e146392011-09-15 23:52:55 +000097 };
Michał Żygowski5c9f5422021-06-16 15:13:54 +020098 struct { /* new since Tiger Point */
99 uint32_t :2,
100 CSSO :10, /* CPU Soft Strap Offset from PMC Base */
101 :4,
102 CSSL :8, /* CPU Soft Strap Length */
103 :8;
104 };
Stefan Tauner1e146392011-09-15 23:52:55 +0000105 };
106};
107
108struct ich_desc_component {
109 union { /* 0x00 */
110 uint32_t FLCOMP; /* Flash Components Register */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000111 /* FLCOMP encoding on various generations:
112 *
113 * Chipset/Generation max_speed dual_output density
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200114 * [MHz] bits max. bits
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000115 * ICH8: 33 N/A 5 0:2, 3:5
116 * ICH9: 33 N/A 5 0:2, 3:5
117 * ICH10: 33 N/A 5 0:2, 3:5
118 * Ibex Peak/5: 50 N/A 5 0:2, 3:5
119 * Cougar Point/6: 50 30 5 0:2, 3:5
120 * Patsburg: 50 30 5 0:2, 3:5
121 * Panther Point/7 50 30 5 0:2, 3:5
122 * Lynx Point/8: 50 30 7 0:3, 4:7
Nico Huberfa622942017-03-24 17:25:37 +0100123 * Wildcat Point/9: 50 30 (multi I/O) 7 0:3, 4:7
124 * Sunrise Point/100: 48 30 7 0:3, 4:7
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000125 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000126 struct {
Duncan Laurie823096e2014-08-20 15:39:38 +0000127 uint32_t :17,
Stefan Tauner1e146392011-09-15 23:52:55 +0000128 freq_read :3,
129 fastread :1,
130 freq_fastread :3,
131 freq_write :3,
132 freq_read_id :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000133 dual_output :1, /* new since Cougar Point/6 */
134 :1;
135 } modes;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000136 struct {
137 uint32_t comp1_density :3,
138 comp2_density :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000139 :26;
140 } dens_old;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000141 struct {
142 uint32_t comp1_density :4, /* new since Lynx Point/8 */
143 comp2_density :4,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000144 :24;
145 } dens_new;
Stefan Tauner1e146392011-09-15 23:52:55 +0000146 };
147 union { /* 0x04 */
148 uint32_t FLILL; /* Flash Invalid Instructions Register */
149 struct {
150 uint32_t invalid_instr0 :8,
151 invalid_instr1 :8,
152 invalid_instr2 :8,
153 invalid_instr3 :8;
154 };
155 };
156 union { /* 0x08 */
Nico Huberfa622942017-03-24 17:25:37 +0100157 uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000158 struct {
159 uint32_t FPBA :13, /* Flash Partition Boundary Addr */
160 :19;
161 };
Nico Huberfa622942017-03-24 17:25:37 +0100162 uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000163 struct {
Nico Huberfa622942017-03-24 17:25:37 +0100164 uint32_t invalid_instr4 :8,
165 invalid_instr5 :8,
166 invalid_instr6 :8,
167 invalid_instr7 :8;
Stefan Tauner1e146392011-09-15 23:52:55 +0000168 };
169 };
170};
171
David Hendricks8e762302017-08-09 22:21:31 -0700172#define MAX_NUM_FLREGS 16
Nico Huberfa622942017-03-24 17:25:37 +0100173struct ich_desc_region {
174 /*
175 * Number of entries and width differ on various generations:
176 *
177 * Chipset/Generation #FLREGs width (bits)
178 * ICH8 .. Panther Point/7 5 13
179 * Lynx Point/8 .. Wildcat Point/9 7 15
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200180 * Sunrise Point/100 .. 200 Series 10 15
David Hendricks8e762302017-08-09 22:21:31 -0700181 * Lewisburg/100 .. 16 15
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200182 * Cannon Point/300 .. 16 15
Nico Huberfa622942017-03-24 17:25:37 +0100183 */
184 union {
185 uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */
186
187 /* only used for bit-field check */
188 struct {
189 uint32_t base :13,
190 :3,
191 limit :13,
192 :3;
193 } old_reg[MAX_NUM_FLREGS];
194 };
195};
196
David Hendricks8e762302017-08-09 22:21:31 -0700197#define MAX_NUM_MASTERS 6 /* 5 prior to C620/Lewisburg PCH */
Stefan Tauner1e146392011-09-15 23:52:55 +0000198struct ich_desc_master {
199 union {
Nico Huberfa622942017-03-24 17:25:37 +0100200 uint32_t FLMSTRs[MAX_NUM_MASTERS]; /* Flash Masters */
201 /* For pre-Skylake platforms */
Stefan Tauner1e146392011-09-15 23:52:55 +0000202 struct {
203 uint32_t BIOS_req_ID :16,
204 BIOS_descr_r :1,
205 BIOS_BIOS_r :1,
206 BIOS_ME_r :1,
207 BIOS_GbE_r :1,
208 BIOS_plat_r :1,
209 :3,
210 BIOS_descr_w :1,
211 BIOS_BIOS_w :1,
212 BIOS_ME_w :1,
213 BIOS_GbE_w :1,
214 BIOS_plat_w :1,
215 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000216 uint32_t ME_req_ID :16,
217 ME_descr_r :1,
218 ME_BIOS_r :1,
219 ME_ME_r :1,
220 ME_GbE_r :1,
221 ME_plat_r :1,
222 :3,
223 ME_descr_w :1,
224 ME_BIOS_w :1,
225 ME_ME_w :1,
226 ME_GbE_w :1,
227 ME_plat_w :1,
228 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000229 uint32_t GbE_req_ID :16,
230 GbE_descr_r :1,
231 GbE_BIOS_r :1,
232 GbE_ME_r :1,
233 GbE_GbE_r :1,
234 GbE_plat_r :1,
235 :3,
236 GbE_descr_w :1,
237 GbE_BIOS_w :1,
238 GbE_ME_w :1,
239 GbE_GbE_w :1,
240 GbE_plat_w :1,
241 :3;
242 };
Nico Huberfa622942017-03-24 17:25:37 +0100243 /* From Skylake on */
244 struct {
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200245 uint32_t ext_read :4,
246 ext_write :4,
247 read :12,
248 write :12;
Nico Huberfa622942017-03-24 17:25:37 +0100249 } mstr[MAX_NUM_MASTERS];
Stefan Tauner1e146392011-09-15 23:52:55 +0000250 };
251};
252
Stefan Taunerb3850962011-12-24 00:00:32 +0000253struct ich_desc_north_strap {
254 union {
255 uint32_t STRPs[1]; /* current maximum: ich8 */
256 struct { /* ich8 */
257 struct { /* STRP2 (in the datasheet) */
258 uint32_t MDB :1,
259 :31;
260 };
261 } ich8;
262 };
263};
264
265struct ich_desc_south_strap {
266 union {
Angel Pons4db0fdf2020-07-10 17:04:10 +0200267 uint32_t STRPs[23]; /* current maximum: gemini lake */
Stefan Taunerb3850962011-12-24 00:00:32 +0000268 struct { /* ich8 */
269 struct { /* STRP1 */
270 uint32_t ME_DISABLE :1,
271 :6,
272 TCOMODE :1,
273 ASD :7,
274 BMCMODE :1,
275 :3,
276 GLAN_PCIE_SEL :1,
277 GPIO12_SEL :2,
278 SPICS1_LANPHYPC_SEL :1,
279 MESM2SEL :1,
280 :1,
281 ASD2 :7;
282 };
283 } ich8;
284 struct { /* ibex peak */
285 struct { /* STRP0 */
286 uint32_t :1,
287 cs_ss2 :1,
288 :5,
289 SMB_EN :1,
290 SML0_EN :1,
291 SML1_EN :1,
292 SML1FRQ :2,
293 SMB0FRQ :2,
294 SML0FRQ :2,
295 :4,
296 LANPHYPC_GP12_SEL :1,
297 cs_ss1 :1,
298 :2,
299 DMI_REQID_DIS :1,
300 :4,
301 BBBS :2,
302 :1;
303 };
304 struct { /* STRP1 */
305 uint32_t cs_ss3 :4,
306 :28;
307 };
308 struct { /* STRP2 */
309 uint32_t :8,
310 MESMASDEN :1,
311 MESMASDA :7,
312 :8,
313 MESMI2CEN :1,
314 MESMI2CA :7;
315 };
316 struct { /* STRP3 */
317 uint32_t :32;
318 };
319 struct { /* STRP4 */
320 uint32_t PHYCON :2,
321 :6,
322 GBEMAC_SMBUS_ADDR_EN :1,
323 GBEMAC_SMBUS_ADDR :7,
324 :1,
325 GBEPHY_SMBUS_ADDR :7,
326 :8;
327 };
328 struct { /* STRP5 */
329 uint32_t :32;
330 };
331 struct { /* STRP6 */
332 uint32_t :32;
333 };
334 struct { /* STRP7 */
335 uint32_t MESMA2UDID_VENDOR :16,
336 MESMA2UDID_DEVICE :16;
337 };
338 struct { /* STRP8 */
339 uint32_t :32;
340 };
341 struct { /* STRP9 */
342 uint32_t PCIEPCS1 :2,
343 PCIEPCS2 :2,
344 PCIELR1 :1,
345 PCIELR2 :1,
346 DMILR :1,
347 :1,
348 PHY_PCIEPORTSEL :3,
349 PHY_PCIE_EN :1,
350 :20;
351 };
352 struct { /* STRP10 */
353 uint32_t :1,
354 ME_BOOT_FLASH :1,
355 cs_ss5 :1,
356 VE_EN :1,
357 :4,
358 MMDDE :1,
359 MMADDR :7,
360 cs_ss7 :1,
361 :1,
362 ICC_SEL :3,
363 MER_CL1 :1,
364 :10;
365 };
366 struct { /* STRP11 */
367 uint32_t SML1GPAEN :1,
368 SML1GPA :7,
369 :16,
370 SML1I2CAEN :1,
371 SML1I2CA :7;
372 };
373 struct { /* STRP12 */
374 uint32_t :32;
375 };
376 struct { /* STRP13 */
377 uint32_t :32;
378 };
379 struct { /* STRP14 */
380 uint32_t :8,
381 VE_EN2 :1,
382 :5,
383 VE_BOOT_FLASH :1,
384 :1,
385 BW_SSD :1,
386 NVMHCI_EN :1,
387 :14;
388 };
389 struct { /* STRP15 */
390 uint32_t :3,
391 cs_ss6 :2,
392 :1,
393 IWL_EN :1,
394 :1,
395 t209min :2,
396 :22;
397 };
398 } ibex;
399 struct { /* cougar point */
400 struct { /* STRP0 */
401 uint32_t :1,
402 cs_ss1 :1,
403 :5,
404 SMB_EN :1,
405 SML0_EN :1,
406 SML1_EN :1,
407 SML1FRQ :2,
408 SMB0FRQ :2,
409 SML0FRQ :2,
410 :4,
411 LANPHYPC_GP12_SEL :1,
412 LINKSEC_DIS :1,
413 :2,
414 DMI_REQID_DIS :1,
415 :4,
416 BBBS :2,
417 :1;
418 };
419 struct { /* STRP1 */
420 uint32_t cs_ss3 :4,
421 :4,
422 cs_ss2 :1,
423 :28;
424 };
425 struct { /* STRP2 */
426 uint32_t :8,
427 MESMASDEN :1,
428 MESMASDA :7,
429 MESMMCTPAEN :1,
430 MESMMCTPA :7,
431 MESMI2CEN :1,
432 MESMI2CA :7;
433 };
434 struct { /* STRP3 */
435 uint32_t :32;
436 };
437 struct { /* STRP4 */
438 uint32_t PHYCON :2,
439 :6,
440 GBEMAC_SMBUS_ADDR_EN :1,
441 GBEMAC_SMBUS_ADDR :7,
442 :1,
443 GBEPHY_SMBUS_ADDR :7,
444 :8;
445 };
446 struct { /* STRP5 */
447 uint32_t :32;
448 };
449 struct { /* STRP6 */
450 uint32_t :32;
451 };
452 struct { /* STRP7 */
453 uint32_t MESMA2UDID_VENDOR :16,
454 MESMA2UDID_DEVICE :16;
455 };
456 struct { /* STRP8 */
457 uint32_t :32;
458 };
459 struct { /* STRP9 */
460 uint32_t PCIEPCS1 :2,
461 PCIEPCS2 :2,
462 PCIELR1 :1,
463 PCIELR2 :1,
464 DMILR :1,
465 cs_ss4 :1,
466 PHY_PCIEPORTSEL :3,
467 PHY_PCIE_EN :1,
468 :2,
469 SUB_DECODE_EN :1,
470 :7,
471 PCHHOT_SML1ALERT_SEL :1,
472 :9;
473 };
474 struct { /* STRP10 */
475 uint32_t :1,
476 ME_BOOT_FLASH :1,
477 :6,
478 MDSMBE_EN :1,
479 MDSMBE_ADD :7,
480 :2,
481 ICC_SEL :3,
482 MER_CL1 :1,
483 ICC_PRO_SEL :1,
484 Deep_SX_EN :1,
485 ME_DBG_LAN :1,
486 :7;
487 };
488 struct { /* STRP11 */
489 uint32_t SML1GPAEN :1,
490 SML1GPA :7,
491 :16,
492 SML1I2CAEN :1,
493 SML1I2CA :7;
494 };
495 struct { /* STRP12 */
496 uint32_t :32;
497 };
498 struct { /* STRP13 */
499 uint32_t :32;
500 };
501 struct { /* STRP14 */
502 uint32_t :32;
503 };
504 struct { /* STRP15 */
505 uint32_t cs_ss6 :6,
506 IWL_EN :1,
507 cs_ss5 :2,
508 :4,
509 SMLINK1_THERM_SEL :1,
510 SLP_LAN_GP29_SEL :1,
511 :16;
512 };
513 struct { /* STRP16 */
514 uint32_t :32;
515 };
516 struct { /* STRP17 */
517 uint32_t ICML :1,
518 cs_ss7 :1,
519 :30;
520 };
521 } cougar;
522 };
523};
524
525struct ich_desc_upper_map {
526 union {
527 uint32_t FLUMAP1; /* Flash Upper Map 1 */
528 struct {
529 uint32_t VTBA :8, /* ME VSCC Table Base Address */
530 VTL :8, /* ME VSCC Table Length */
Nico Huber3ad9aad2021-06-17 22:05:00 +0200531 :8,
532 MDTBA :8; /* MIP Descr. Table Base Addr. (new since Cannon Point/300) */
Stefan Taunerb3850962011-12-24 00:00:32 +0000533 };
534 };
535 struct {
536 union { /* JEDEC-ID Register */
537 uint32_t JID;
538 struct {
539 uint32_t vid :8, /* Vendor ID */
540 cid0 :8, /* Component ID 0 */
541 cid1 :8, /* Component ID 1 */
542 :8;
543 };
544 };
545 union { /* Vendor Specific Component Capabilities */
546 uint32_t VSCC;
547 struct {
548 uint32_t ubes :2, /* Upper Block/Sector Erase Size */
549 uwg :1, /* Upper Write Granularity */
550 uwsr :1, /* Upper Write Status Required */
551 uwews :1, /* Upper Write Enable on Write Status */
552 :3,
553 ueo :8, /* Upper Erase Opcode */
554 lbes :2, /* Lower Block/Sector Erase Size */
555 lwg :1, /* Lower Write Granularity */
556 lwsr :1, /* Lower Write Status Required */
557 lwews :1, /* Lower Write Enable on Write Status */
558 :3,
559 leo :16; /* Lower Erase Opcode */
560 };
561 };
562 } vscc_table[128];
563};
Stefan Taunerb3850962011-12-24 00:00:32 +0000564
Stefan Tauner1e146392011-09-15 23:52:55 +0000565struct ich_descriptors {
566 struct ich_desc_content content;
567 struct ich_desc_component component;
568 struct ich_desc_region region;
569 struct ich_desc_master master;
Stefan Taunerb3850962011-12-24 00:00:32 +0000570 struct ich_desc_north_strap north;
571 struct ich_desc_south_strap south;
572 struct ich_desc_upper_map upper;
Stefan Tauner1e146392011-09-15 23:52:55 +0000573};
574
David Hendricks0eb00d42017-09-01 20:02:36 -0700575struct ich_layout {
576 struct flashrom_layout base;
David Hendricks7a8305f2017-09-01 20:16:58 -0700577 struct romentry entries[MAX_NUM_FLREGS];
David Hendricks0eb00d42017-09-01 20:02:36 -0700578};
579
Nico Huberfa622942017-03-24 17:25:37 +0100580ssize_t ich_number_of_regions(enum ich_chipset cs, const struct ich_desc_content *content);
581ssize_t ich_number_of_masters(enum ich_chipset cs, const struct ich_desc_content *content);
582
Nico Huber67d71792017-06-17 03:10:15 +0200583void prettyprint_ich_chipset(enum ich_chipset cs);
Stefan Taunerb3850962011-12-24 00:00:32 +0000584void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000585
Nico Huberfa622942017-03-24 17:25:37 +0100586void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *content);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000587void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100588void prettyprint_ich_descriptor_region(enum ich_chipset cs, const struct ich_descriptors *desc);
589void prettyprint_ich_descriptor_master(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000590
Stefan Taunerb3850962011-12-24 00:00:32 +0000591void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
592void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100593int read_ich_descriptors_from_dump(const uint32_t *dump, size_t len, enum ich_chipset *cs, struct ich_descriptors *desc);
Stefan Taunerb3850962011-12-24 00:00:32 +0000594
Nico Huberd54e4f42017-03-23 23:45:47 +0100595int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000596int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx);
Stefan Tauner1e146392011-09-15 23:52:55 +0000597
Nico Huber305f4172013-06-14 11:55:26 +0200598int layout_from_ich_descriptors(struct ich_layout *, const void *dump, size_t len);
599
Stefan Tauner1e146392011-09-15 23:52:55 +0000600#endif /* __ICH_DESCRIPTORS_H__ */