blob: b26f533ba7adc71826cfb18f10e4389fb56d0e67 [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the common SPI chip driver functions
23 */
24
25#include <string.h>
26#include "flash.h"
27#include "flashchips.h"
28#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "spi.h"
31
Sean Nelson14ba6682010-02-26 05:48:29 +000032static int spi_rdid(unsigned char *readarr, int bytes)
33{
Mathias Krausea60faab2011-01-17 07:50:42 +000034 static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Sean Nelson14ba6682010-02-26 05:48:29 +000035 int ret;
36 int i;
37
38 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
39 if (ret)
40 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000041 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000042 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000043 msg_cspew(" 0x%02x", readarr[i]);
44 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000045 return 0;
46}
47
48static int spi_rems(unsigned char *readarr)
49{
50 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
51 uint32_t readaddr;
52 int ret;
53
54 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
55 if (ret == SPI_INVALID_ADDRESS) {
56 /* Find the lowest even address allowed for reads. */
57 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
58 cmd[1] = (readaddr >> 16) & 0xff,
59 cmd[2] = (readaddr >> 8) & 0xff,
60 cmd[3] = (readaddr >> 0) & 0xff,
61 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
62 }
63 if (ret)
64 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000065 msg_cspew("REMS returned %02x %02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000066 return 0;
67}
68
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000069static int spi_res(unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000070{
71 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
72 uint32_t readaddr;
73 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000074 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000075
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000076 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000077 if (ret == SPI_INVALID_ADDRESS) {
78 /* Find the lowest even address allowed for reads. */
79 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
80 cmd[1] = (readaddr >> 16) & 0xff,
81 cmd[2] = (readaddr >> 8) & 0xff,
82 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000083 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000084 }
85 if (ret)
86 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000087 msg_cspew("RES returned");
88 for (i = 0; i < bytes; i++)
89 msg_cspew(" 0x%02x", readarr[i]);
90 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000091 return 0;
92}
93
94int spi_write_enable(void)
95{
Mathias Krausea60faab2011-01-17 07:50:42 +000096 static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Sean Nelson14ba6682010-02-26 05:48:29 +000097 int result;
98
99 /* Send WREN (Write Enable) */
100 result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
101
102 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000103 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000104
105 return result;
106}
107
108int spi_write_disable(void)
109{
Mathias Krausea60faab2011-01-17 07:50:42 +0000110 static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Sean Nelson14ba6682010-02-26 05:48:29 +0000111
112 /* Send WRDI (Write Disable) */
113 return spi_send_command(sizeof(cmd), 0, cmd, NULL);
114}
115
116static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
117{
118 unsigned char readarr[4];
119 uint32_t id1;
120 uint32_t id2;
121
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000122 if (spi_rdid(readarr, bytes)) {
123 msg_cdbg("\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000124 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000125 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000126
127 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000128 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000129
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000130 /* Check if this is a continuation vendor ID.
131 * FIXME: Handle continuation device IDs.
132 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000133 if (readarr[0] == 0x7f) {
134 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000135 msg_cdbg("RDID byte 1 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000136 id1 = (readarr[0] << 8) | readarr[1];
137 id2 = readarr[2];
138 if (bytes > 3) {
139 id2 <<= 8;
140 id2 |= readarr[3];
141 }
142 } else {
143 id1 = readarr[0];
144 id2 = (readarr[1] << 8) | readarr[2];
145 }
146
Sean Nelsoned479d22010-03-24 23:14:32 +0000147 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000148
149 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
150 /* Print the status register to tell the
151 * user about possible write protection.
152 */
153 spi_prettyprint_status_register(flash);
154
155 return 1;
156 }
157
158 /* Test if this is a pure vendor match. */
159 if (id1 == flash->manufacture_id &&
160 GENERIC_DEVICE_ID == flash->model_id)
161 return 1;
162
163 /* Test if there is any vendor ID. */
164 if (GENERIC_MANUF_ID == flash->manufacture_id &&
165 id1 != 0xff)
166 return 1;
167
168 return 0;
169}
170
171int probe_spi_rdid(struct flashchip *flash)
172{
173 return probe_spi_rdid_generic(flash, 3);
174}
175
Sean Nelson14ba6682010-02-26 05:48:29 +0000176int probe_spi_rdid4(struct flashchip *flash)
177{
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000178 /* Some SPI controllers do not support commands with writecnt=1 and
179 * readcnt=4.
180 */
Michael Karcherb9dbe482011-05-11 17:07:07 +0000181 switch (spi_programmer->type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000182#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000183#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000184 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +0000185 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000186 msg_cinfo("4 byte RDID not supported on this SPI controller\n");
187 return 0;
188 break;
Sean Nelson14ba6682010-02-26 05:48:29 +0000189#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000190#endif
Sean Nelson14ba6682010-02-26 05:48:29 +0000191 default:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000192 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000193 }
194
195 return 0;
196}
197
198int probe_spi_rems(struct flashchip *flash)
199{
200 unsigned char readarr[JEDEC_REMS_INSIZE];
201 uint32_t id1, id2;
202
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000203 if (spi_rems(readarr)) {
204 msg_cdbg("\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000205 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000206 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000207
208 id1 = readarr[0];
209 id2 = readarr[1];
210
Sean Nelsoned479d22010-03-24 23:14:32 +0000211 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000212
213 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
214 /* Print the status register to tell the
215 * user about possible write protection.
216 */
217 spi_prettyprint_status_register(flash);
218
219 return 1;
220 }
221
222 /* Test if this is a pure vendor match. */
223 if (id1 == flash->manufacture_id &&
224 GENERIC_DEVICE_ID == flash->model_id)
225 return 1;
226
227 /* Test if there is any vendor ID. */
228 if (GENERIC_MANUF_ID == flash->manufacture_id &&
229 id1 != 0xff)
230 return 1;
231
232 return 0;
233}
234
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000235int probe_spi_res1(struct flashchip *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000236{
Mathias Krausea60faab2011-01-17 07:50:42 +0000237 static const unsigned char allff[] = {0xff, 0xff, 0xff};
238 static const unsigned char all00[] = {0x00, 0x00, 0x00};
Sean Nelson14ba6682010-02-26 05:48:29 +0000239 unsigned char readarr[3];
240 uint32_t id2;
Sean Nelson14ba6682010-02-26 05:48:29 +0000241
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000242 /* We only want one-byte RES if RDID and REMS are unusable. */
243
Sean Nelson14ba6682010-02-26 05:48:29 +0000244 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
245 * 0x00 0x00 0x00. In that case, RES is pointless.
246 */
247 if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) &&
248 memcmp(readarr, all00, 3)) {
249 msg_cdbg("Ignoring RES in favour of RDID.\n");
250 return 0;
251 }
252 /* Check if REMS is usable and does not return 0xff 0xff or
253 * 0x00 0x00. In that case, RES is pointless.
254 */
255 if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
256 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
257 msg_cdbg("Ignoring RES in favour of REMS.\n");
258 return 0;
259 }
260
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000261 if (spi_res(readarr, 1)) {
262 msg_cdbg("\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000263 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000264 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000265
Sean Nelson14ba6682010-02-26 05:48:29 +0000266 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000267
Sean Nelsoned479d22010-03-24 23:14:32 +0000268 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000269
Stefan Taunerdb45ab52011-05-28 22:59:05 +0000270 if (id2 != flash->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000271 return 0;
272
273 /* Print the status register to tell the
274 * user about possible write protection.
275 */
276 spi_prettyprint_status_register(flash);
277 return 1;
278}
279
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000280int probe_spi_res2(struct flashchip *flash)
281{
282 unsigned char readarr[2];
283 uint32_t id1, id2;
284
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000285 if (spi_res(readarr, 2)) {
286 msg_cdbg("\n");
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000287 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000288 }
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000289
290 id1 = readarr[0];
291 id2 = readarr[1];
292
293 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
294
295 if (id1 != flash->manufacture_id || id2 != flash->model_id)
296 return 0;
297
298 /* Print the status register to tell the
299 * user about possible write protection.
300 */
301 spi_prettyprint_status_register(flash);
302 return 1;
303}
304
Sean Nelson14ba6682010-02-26 05:48:29 +0000305uint8_t spi_read_status_register(void)
306{
Mathias Krausea60faab2011-01-17 07:50:42 +0000307 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
Sean Nelson14ba6682010-02-26 05:48:29 +0000308 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
309 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
310 int ret;
311
312 /* Read Status Register */
313 ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
314 if (ret)
Sean Nelsoned479d22010-03-24 23:14:32 +0000315 msg_cerr("RDSR failed!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000316
317 return readarr[0];
318}
319
320/* Prettyprint the status register. Common definitions. */
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000321void spi_prettyprint_status_register_welwip(uint8_t status)
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000322{
323 msg_cdbg("Chip status register: Write Enable Latch (WEL) is "
324 "%sset\n", (status & (1 << 1)) ? "" : "not ");
325 msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is "
326 "%sset\n", (status & (1 << 0)) ? "" : "not ");
327}
328
329/* Prettyprint the status register. Common definitions. */
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000330void spi_prettyprint_status_register_bp3210(uint8_t status, int bp)
331{
332 switch (bp) {
333 /* Fall through. */
334 case 3:
335 msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) "
336 "is %sset\n", (status & (1 << 5)) ? "" : "not ");
337 case 2:
338 msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) "
339 "is %sset\n", (status & (1 << 4)) ? "" : "not ");
340 case 1:
341 msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) "
342 "is %sset\n", (status & (1 << 3)) ? "" : "not ");
343 case 0:
344 msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) "
345 "is %sset\n", (status & (1 << 2)) ? "" : "not ");
346 }
347}
348
349/* Prettyprint the status register. Unnamed bits. */
350void spi_prettyprint_status_register_bit(uint8_t status, int bit)
351{
352 msg_cdbg("Chip status register: Bit %i "
353 "is %sset\n", bit, (status & (1 << bit)) ? "" : "not ");
354}
355
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000356static void spi_prettyprint_status_register_common(uint8_t status)
Sean Nelson14ba6682010-02-26 05:48:29 +0000357{
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000358 spi_prettyprint_status_register_bp3210(status, 3);
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000359 spi_prettyprint_status_register_welwip(status);
Sean Nelson14ba6682010-02-26 05:48:29 +0000360}
361
362/* Prettyprint the status register. Works for
363 * ST M25P series
364 * MX MX25L series
365 */
366void spi_prettyprint_status_register_st_m25p(uint8_t status)
367{
Sean Nelsoned479d22010-03-24 23:14:32 +0000368 msg_cdbg("Chip status register: Status Register Write Disable "
Sean Nelson14ba6682010-02-26 05:48:29 +0000369 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000370 msg_cdbg("Chip status register: Bit 6 is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000371 "%sset\n", (status & (1 << 6)) ? "" : "not ");
372 spi_prettyprint_status_register_common(status);
373}
374
375void spi_prettyprint_status_register_sst25(uint8_t status)
376{
Sean Nelsoned479d22010-03-24 23:14:32 +0000377 msg_cdbg("Chip status register: Block Protect Write Disable "
Sean Nelson14ba6682010-02-26 05:48:29 +0000378 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000379 msg_cdbg("Chip status register: Auto Address Increment Programming "
Sean Nelson14ba6682010-02-26 05:48:29 +0000380 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
381 spi_prettyprint_status_register_common(status);
382}
383
384/* Prettyprint the status register. Works for
385 * SST 25VF016
386 */
387void spi_prettyprint_status_register_sst25vf016(uint8_t status)
388{
Mathias Krausea60faab2011-01-17 07:50:42 +0000389 static const char *const bpt[] = {
Sean Nelson14ba6682010-02-26 05:48:29 +0000390 "none",
391 "1F0000H-1FFFFFH",
392 "1E0000H-1FFFFFH",
393 "1C0000H-1FFFFFH",
394 "180000H-1FFFFFH",
395 "100000H-1FFFFFH",
396 "all", "all"
397 };
398 spi_prettyprint_status_register_sst25(status);
Sean Nelsoned479d22010-03-24 23:14:32 +0000399 msg_cdbg("Resulting block protection : %s\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000400 bpt[(status & 0x1c) >> 2]);
401}
402
403void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
404{
Mathias Krausea60faab2011-01-17 07:50:42 +0000405 static const char *const bpt[] = {
Sean Nelson14ba6682010-02-26 05:48:29 +0000406 "none",
407 "0x70000-0x7ffff",
408 "0x60000-0x7ffff",
409 "0x40000-0x7ffff",
410 "all blocks", "all blocks", "all blocks", "all blocks"
411 };
412 spi_prettyprint_status_register_sst25(status);
Sean Nelsoned479d22010-03-24 23:14:32 +0000413 msg_cdbg("Resulting block protection : %s\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000414 bpt[(status & 0x1c) >> 2]);
415}
416
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000417int spi_prettyprint_status_register(struct flashchip *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000418{
419 uint8_t status;
420
421 status = spi_read_status_register();
Sean Nelsoned479d22010-03-24 23:14:32 +0000422 msg_cdbg("Chip status register is %02x\n", status);
Sean Nelson14ba6682010-02-26 05:48:29 +0000423 switch (flash->manufacture_id) {
424 case ST_ID:
425 if (((flash->model_id & 0xff00) == 0x2000) ||
426 ((flash->model_id & 0xff00) == 0x2500))
427 spi_prettyprint_status_register_st_m25p(status);
428 break;
Mattias Mattsson6eabe282010-09-15 23:31:03 +0000429 case MACRONIX_ID:
Sean Nelson14ba6682010-02-26 05:48:29 +0000430 if ((flash->model_id & 0xff00) == 0x2000)
431 spi_prettyprint_status_register_st_m25p(status);
432 break;
433 case SST_ID:
434 switch (flash->model_id) {
435 case 0x2541:
436 spi_prettyprint_status_register_sst25vf016(status);
437 break;
438 case 0x8d:
439 case 0x258d:
440 spi_prettyprint_status_register_sst25vf040b(status);
441 break;
442 default:
443 spi_prettyprint_status_register_sst25(status);
444 break;
445 }
446 break;
447 }
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000448 return 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000449}
450
451int spi_chip_erase_60(struct flashchip *flash)
452{
453 int result;
454 struct spi_command cmds[] = {
455 {
456 .writecnt = JEDEC_WREN_OUTSIZE,
457 .writearr = (const unsigned char[]){ JEDEC_WREN },
458 .readcnt = 0,
459 .readarr = NULL,
460 }, {
461 .writecnt = JEDEC_CE_60_OUTSIZE,
462 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
463 .readcnt = 0,
464 .readarr = NULL,
465 }, {
466 .writecnt = 0,
467 .writearr = NULL,
468 .readcnt = 0,
469 .readarr = NULL,
470 }};
471
Sean Nelson14ba6682010-02-26 05:48:29 +0000472 result = spi_send_multicommand(cmds);
473 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000474 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000475 __func__);
476 return result;
477 }
478 /* Wait until the Write-In-Progress bit is cleared.
479 * This usually takes 1-85 s, so wait in 1 s steps.
480 */
481 /* FIXME: We assume spi_read_status_register will never fail. */
482 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
483 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000484 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000485 return 0;
486}
487
488int spi_chip_erase_c7(struct flashchip *flash)
489{
490 int result;
491 struct spi_command cmds[] = {
492 {
493 .writecnt = JEDEC_WREN_OUTSIZE,
494 .writearr = (const unsigned char[]){ JEDEC_WREN },
495 .readcnt = 0,
496 .readarr = NULL,
497 }, {
498 .writecnt = JEDEC_CE_C7_OUTSIZE,
499 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
500 .readcnt = 0,
501 .readarr = NULL,
502 }, {
503 .writecnt = 0,
504 .writearr = NULL,
505 .readcnt = 0,
506 .readarr = NULL,
507 }};
508
Sean Nelson14ba6682010-02-26 05:48:29 +0000509 result = spi_send_multicommand(cmds);
510 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000511 msg_cerr("%s failed during command execution\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000512 return result;
513 }
514 /* Wait until the Write-In-Progress bit is cleared.
515 * This usually takes 1-85 s, so wait in 1 s steps.
516 */
517 /* FIXME: We assume spi_read_status_register will never fail. */
518 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
519 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000520 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000521 return 0;
522}
523
Sean Nelson14ba6682010-02-26 05:48:29 +0000524int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
525{
526 int result;
527 struct spi_command cmds[] = {
528 {
529 .writecnt = JEDEC_WREN_OUTSIZE,
530 .writearr = (const unsigned char[]){ JEDEC_WREN },
531 .readcnt = 0,
532 .readarr = NULL,
533 }, {
534 .writecnt = JEDEC_BE_52_OUTSIZE,
535 .writearr = (const unsigned char[]){
536 JEDEC_BE_52,
537 (addr >> 16) & 0xff,
538 (addr >> 8) & 0xff,
539 (addr & 0xff)
540 },
541 .readcnt = 0,
542 .readarr = NULL,
543 }, {
544 .writecnt = 0,
545 .writearr = NULL,
546 .readcnt = 0,
547 .readarr = NULL,
548 }};
549
550 result = spi_send_multicommand(cmds);
551 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000552 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000553 __func__, addr);
554 return result;
555 }
556 /* Wait until the Write-In-Progress bit is cleared.
557 * This usually takes 100-4000 ms, so wait in 100 ms steps.
558 */
559 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
560 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000561 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000562 return 0;
563}
564
565/* Block size is usually
566 * 64k for Macronix
567 * 32k for SST
568 * 4-32k non-uniform for EON
569 */
570int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
571{
572 int result;
573 struct spi_command cmds[] = {
574 {
575 .writecnt = JEDEC_WREN_OUTSIZE,
576 .writearr = (const unsigned char[]){ JEDEC_WREN },
577 .readcnt = 0,
578 .readarr = NULL,
579 }, {
580 .writecnt = JEDEC_BE_D8_OUTSIZE,
581 .writearr = (const unsigned char[]){
582 JEDEC_BE_D8,
583 (addr >> 16) & 0xff,
584 (addr >> 8) & 0xff,
585 (addr & 0xff)
586 },
587 .readcnt = 0,
588 .readarr = NULL,
589 }, {
590 .writecnt = 0,
591 .writearr = NULL,
592 .readcnt = 0,
593 .readarr = NULL,
594 }};
595
596 result = spi_send_multicommand(cmds);
597 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000598 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000599 __func__, addr);
600 return result;
601 }
602 /* Wait until the Write-In-Progress bit is cleared.
603 * This usually takes 100-4000 ms, so wait in 100 ms steps.
604 */
605 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
606 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000607 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000608 return 0;
609}
610
611/* Block size is usually
612 * 4k for PMC
613 */
614int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
615{
616 int result;
617 struct spi_command cmds[] = {
618 {
619 .writecnt = JEDEC_WREN_OUTSIZE,
620 .writearr = (const unsigned char[]){ JEDEC_WREN },
621 .readcnt = 0,
622 .readarr = NULL,
623 }, {
624 .writecnt = JEDEC_BE_D7_OUTSIZE,
625 .writearr = (const unsigned char[]){
626 JEDEC_BE_D7,
627 (addr >> 16) & 0xff,
628 (addr >> 8) & 0xff,
629 (addr & 0xff)
630 },
631 .readcnt = 0,
632 .readarr = NULL,
633 }, {
634 .writecnt = 0,
635 .writearr = NULL,
636 .readcnt = 0,
637 .readarr = NULL,
638 }};
639
640 result = spi_send_multicommand(cmds);
641 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000642 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000643 __func__, addr);
644 return result;
645 }
646 /* Wait until the Write-In-Progress bit is cleared.
647 * This usually takes 100-4000 ms, so wait in 100 ms steps.
648 */
649 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
650 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000651 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000652 return 0;
653}
654
Sean Nelson14ba6682010-02-26 05:48:29 +0000655/* Sector size is usually 4k, though Macronix eliteflash has 64k */
656int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
657{
658 int result;
659 struct spi_command cmds[] = {
660 {
661 .writecnt = JEDEC_WREN_OUTSIZE,
662 .writearr = (const unsigned char[]){ JEDEC_WREN },
663 .readcnt = 0,
664 .readarr = NULL,
665 }, {
666 .writecnt = JEDEC_SE_OUTSIZE,
667 .writearr = (const unsigned char[]){
668 JEDEC_SE,
669 (addr >> 16) & 0xff,
670 (addr >> 8) & 0xff,
671 (addr & 0xff)
672 },
673 .readcnt = 0,
674 .readarr = NULL,
675 }, {
676 .writecnt = 0,
677 .writearr = NULL,
678 .readcnt = 0,
679 .readarr = NULL,
680 }};
681
682 result = spi_send_multicommand(cmds);
683 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000684 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000685 __func__, addr);
686 return result;
687 }
688 /* Wait until the Write-In-Progress bit is cleared.
689 * This usually takes 15-800 ms, so wait in 10 ms steps.
690 */
691 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
692 programmer_delay(10 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000693 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000694 return 0;
695}
696
697int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
698{
699 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000700 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000701 __func__);
702 return -1;
703 }
704 return spi_chip_erase_60(flash);
705}
706
707int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
708{
709 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000710 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000711 __func__);
712 return -1;
713 }
714 return spi_chip_erase_c7(flash);
715}
716
717int spi_write_status_enable(void)
718{
Mathias Krausea60faab2011-01-17 07:50:42 +0000719 static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
Sean Nelson14ba6682010-02-26 05:48:29 +0000720 int result;
721
722 /* Send EWSR (Enable Write Status Register). */
723 result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
724
725 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000726 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000727
728 return result;
729}
730
731/*
732 * This is according the SST25VF016 datasheet, who knows it is more
733 * generic that this...
734 */
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000735static int spi_write_status_register_ewsr(struct flashchip *flash, int status)
Sean Nelson14ba6682010-02-26 05:48:29 +0000736{
737 int result;
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000738 int i = 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000739 struct spi_command cmds[] = {
740 {
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000741 /* WRSR requires either EWSR or WREN depending on chip type. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000742 .writecnt = JEDEC_EWSR_OUTSIZE,
743 .writearr = (const unsigned char[]){ JEDEC_EWSR },
744 .readcnt = 0,
745 .readarr = NULL,
746 }, {
747 .writecnt = JEDEC_WRSR_OUTSIZE,
748 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
749 .readcnt = 0,
750 .readarr = NULL,
751 }, {
752 .writecnt = 0,
753 .writearr = NULL,
754 .readcnt = 0,
755 .readarr = NULL,
756 }};
757
758 result = spi_send_multicommand(cmds);
759 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000760 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000761 __func__);
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000762 /* No point in waiting for the command to complete if execution
763 * failed.
764 */
765 return result;
Sean Nelson14ba6682010-02-26 05:48:29 +0000766 }
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000767 /* WRSR performs a self-timed erase before the changes take effect.
768 * This may take 50-85 ms in most cases, and some chips apparently
769 * allow running RDSR only once. Therefore pick an initial delay of
770 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
771 */
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000772 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000773 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
774 if (++i > 490) {
775 msg_cerr("Error: WIP bit after WRSR never cleared\n");
776 return TIMEOUT_ERROR;
777 }
778 programmer_delay(10 * 1000);
779 }
780 return 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000781}
782
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000783static int spi_write_status_register_wren(struct flashchip *flash, int status)
784{
785 int result;
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000786 int i = 0;
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000787 struct spi_command cmds[] = {
788 {
789 /* WRSR requires either EWSR or WREN depending on chip type. */
790 .writecnt = JEDEC_WREN_OUTSIZE,
791 .writearr = (const unsigned char[]){ JEDEC_WREN },
792 .readcnt = 0,
793 .readarr = NULL,
794 }, {
795 .writecnt = JEDEC_WRSR_OUTSIZE,
796 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
797 .readcnt = 0,
798 .readarr = NULL,
799 }, {
800 .writecnt = 0,
801 .writearr = NULL,
802 .readcnt = 0,
803 .readarr = NULL,
804 }};
805
806 result = spi_send_multicommand(cmds);
807 if (result) {
808 msg_cerr("%s failed during command execution\n",
809 __func__);
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000810 /* No point in waiting for the command to complete if execution
811 * failed.
812 */
813 return result;
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000814 }
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000815 /* WRSR performs a self-timed erase before the changes take effect.
816 * This may take 50-85 ms in most cases, and some chips apparently
817 * allow running RDSR only once. Therefore pick an initial delay of
818 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
819 */
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000820 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger174f55b2010-10-08 00:37:55 +0000821 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
822 if (++i > 490) {
823 msg_cerr("Error: WIP bit after WRSR never cleared\n");
824 return TIMEOUT_ERROR;
825 }
826 programmer_delay(10 * 1000);
827 }
828 return 0;
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000829}
830
Carl-Daniel Hailfinger7a3bd8f2011-05-19 00:06:06 +0000831int spi_write_status_register(struct flashchip *flash, int status)
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000832{
833 int ret = 1;
834
835 if (!(flash->feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
836 msg_cdbg("Missing status register write definition, assuming "
837 "EWSR is needed\n");
838 flash->feature_bits |= FEATURE_WRSR_EWSR;
839 }
840 if (flash->feature_bits & FEATURE_WRSR_WREN)
841 ret = spi_write_status_register_wren(flash, status);
842 if (ret && (flash->feature_bits & FEATURE_WRSR_EWSR))
843 ret = spi_write_status_register_ewsr(flash, status);
844 return ret;
845}
846
Sean Nelson14ba6682010-02-26 05:48:29 +0000847int spi_byte_program(int addr, uint8_t databyte)
848{
849 int result;
850 struct spi_command cmds[] = {
851 {
852 .writecnt = JEDEC_WREN_OUTSIZE,
853 .writearr = (const unsigned char[]){ JEDEC_WREN },
854 .readcnt = 0,
855 .readarr = NULL,
856 }, {
857 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
858 .writearr = (const unsigned char[]){
859 JEDEC_BYTE_PROGRAM,
860 (addr >> 16) & 0xff,
861 (addr >> 8) & 0xff,
862 (addr & 0xff),
863 databyte
864 },
865 .readcnt = 0,
866 .readarr = NULL,
867 }, {
868 .writecnt = 0,
869 .writearr = NULL,
870 .readcnt = 0,
871 .readarr = NULL,
872 }};
873
874 result = spi_send_multicommand(cmds);
875 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000876 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000877 __func__, addr);
878 }
879 return result;
880}
881
882int spi_nbyte_program(int addr, uint8_t *bytes, int len)
883{
884 int result;
885 /* FIXME: Switch to malloc based on len unless that kills speed. */
886 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
887 JEDEC_BYTE_PROGRAM,
888 (addr >> 16) & 0xff,
889 (addr >> 8) & 0xff,
890 (addr >> 0) & 0xff,
891 };
892 struct spi_command cmds[] = {
893 {
894 .writecnt = JEDEC_WREN_OUTSIZE,
895 .writearr = (const unsigned char[]){ JEDEC_WREN },
896 .readcnt = 0,
897 .readarr = NULL,
898 }, {
899 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
900 .writearr = cmd,
901 .readcnt = 0,
902 .readarr = NULL,
903 }, {
904 .writecnt = 0,
905 .writearr = NULL,
906 .readcnt = 0,
907 .readarr = NULL,
908 }};
909
910 if (!len) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000911 msg_cerr("%s called for zero-length write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000912 return 1;
913 }
914 if (len > 256) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000915 msg_cerr("%s called for too long a write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000916 return 1;
917 }
918
919 memcpy(&cmd[4], bytes, len);
920
921 result = spi_send_multicommand(cmds);
922 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000923 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000924 __func__, addr);
925 }
926 return result;
927}
928
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000929/* A generic brute-force block protection disable works like this:
930 * Write 0x00 to the status register. Check if any locks are still set (that
931 * part is chip specific). Repeat once.
932 */
Carl-Daniel Hailfinger29a1c662010-07-14 20:21:22 +0000933int spi_disable_blockprotect(struct flashchip *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000934{
935 uint8_t status;
936 int result;
937
938 status = spi_read_status_register();
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000939 /* If block protection is disabled, stop here. */
940 if ((status & 0x3c) == 0)
941 return 0;
942
943 msg_cdbg("Some block protection in effect, disabling\n");
944 result = spi_write_status_register(flash, status & ~0x3c);
945 if (result) {
946 msg_cerr("spi_write_status_register failed\n");
947 return result;
948 }
949 status = spi_read_status_register();
Sean Nelson14ba6682010-02-26 05:48:29 +0000950 if ((status & 0x3c) != 0) {
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000951 msg_cerr("Block protection could not be disabled!\n");
952 return 1;
953 }
954 return 0;
955}
956
Sean Nelson14ba6682010-02-26 05:48:29 +0000957int spi_nbyte_read(int address, uint8_t *bytes, int len)
958{
959 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
960 JEDEC_READ,
961 (address >> 16) & 0xff,
962 (address >> 8) & 0xff,
963 (address >> 0) & 0xff,
964 };
965
966 /* Send Read */
967 return spi_send_command(sizeof(cmd), len, cmd, bytes);
968}
969
970/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000971 * Read a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000972 * FIXME: Use the chunk code from Michael Karcher instead.
Sean Nelson14ba6682010-02-26 05:48:29 +0000973 * Each page is read separately in chunks with a maximum size of chunksize.
974 */
975int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
976{
977 int rc = 0;
978 int i, j, starthere, lenhere;
979 int page_size = flash->page_size;
980 int toread;
981
982 /* Warning: This loop has a very unusual condition and body.
983 * The loop needs to go through each page with at least one affected
984 * byte. The lowest page number is (start / page_size) since that
985 * division rounds down. The highest page number we want is the page
986 * where the last byte of the range lives. That last byte has the
987 * address (start + len - 1), thus the highest page number is
988 * (start + len - 1) / page_size. Since we want to include that last
989 * page as well, the loop condition uses <=.
990 */
991 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
992 /* Byte position of the first byte in the range in this page. */
993 /* starthere is an offset to the base address of the chip. */
994 starthere = max(start, i * page_size);
995 /* Length of bytes in the range in this page. */
996 lenhere = min(start + len, (i + 1) * page_size) - starthere;
997 for (j = 0; j < lenhere; j += chunksize) {
998 toread = min(chunksize, lenhere - j);
999 rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
1000 if (rc)
1001 break;
1002 }
1003 if (rc)
1004 break;
1005 }
1006
1007 return rc;
1008}
1009
1010/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00001011 * Write a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001012 * FIXME: Use the chunk code from Michael Karcher instead.
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00001013 * Each page is written separately in chunks with a maximum size of chunksize.
1014 */
1015int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
1016{
1017 int rc = 0;
1018 int i, j, starthere, lenhere;
1019 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
1020 * in struct flashchip to do this properly. All chips using
1021 * spi_chip_write_256 have page_size set to max_writechunk_size, so
1022 * we're OK for now.
1023 */
1024 int page_size = flash->page_size;
1025 int towrite;
1026
1027 /* Warning: This loop has a very unusual condition and body.
1028 * The loop needs to go through each page with at least one affected
1029 * byte. The lowest page number is (start / page_size) since that
1030 * division rounds down. The highest page number we want is the page
1031 * where the last byte of the range lives. That last byte has the
1032 * address (start + len - 1), thus the highest page number is
1033 * (start + len - 1) / page_size. Since we want to include that last
1034 * page as well, the loop condition uses <=.
1035 */
1036 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
1037 /* Byte position of the first byte in the range in this page. */
1038 /* starthere is an offset to the base address of the chip. */
1039 starthere = max(start, i * page_size);
1040 /* Length of bytes in the range in this page. */
1041 lenhere = min(start + len, (i + 1) * page_size) - starthere;
1042 for (j = 0; j < lenhere; j += chunksize) {
1043 towrite = min(chunksize, lenhere - j);
1044 rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite);
1045 if (rc)
1046 break;
1047 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1048 programmer_delay(10);
1049 }
1050 if (rc)
1051 break;
1052 }
1053
1054 return rc;
1055}
1056
1057/*
Sean Nelson14ba6682010-02-26 05:48:29 +00001058 * Program chip using byte programming. (SLOW!)
1059 * This is for chips which can only handle one byte writes
1060 * and for chips where memory mapped programming is impossible
1061 * (e.g. due to size constraints in IT87* for over 512 kB)
1062 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001063/* real chunksize is 1, logical chunksize is 1 */
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001064int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len)
Sean Nelson14ba6682010-02-26 05:48:29 +00001065{
Sean Nelson14ba6682010-02-26 05:48:29 +00001066 int i, result = 0;
1067
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001068 for (i = start; i < start + len; i++) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001069 result = spi_byte_program(i, buf[i - start]);
Sean Nelson14ba6682010-02-26 05:48:29 +00001070 if (result)
1071 return 1;
1072 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1073 programmer_delay(10);
1074 }
1075
1076 return 0;
1077}
1078
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001079int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001080{
1081 uint32_t pos = start;
Sean Nelson14ba6682010-02-26 05:48:29 +00001082 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001083 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
1084 JEDEC_AAI_WORD_PROGRAM,
1085 };
1086 struct spi_command cmds[] = {
1087 {
1088 .writecnt = JEDEC_WREN_OUTSIZE,
1089 .writearr = (const unsigned char[]){ JEDEC_WREN },
1090 .readcnt = 0,
1091 .readarr = NULL,
1092 }, {
1093 .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE,
1094 .writearr = (const unsigned char[]){
1095 JEDEC_AAI_WORD_PROGRAM,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001096 (start >> 16) & 0xff,
1097 (start >> 8) & 0xff,
1098 (start & 0xff),
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001099 buf[0],
1100 buf[1]
1101 },
1102 .readcnt = 0,
1103 .readarr = NULL,
1104 }, {
1105 .writecnt = 0,
1106 .writearr = NULL,
1107 .readcnt = 0,
1108 .readarr = NULL,
1109 }};
Sean Nelson14ba6682010-02-26 05:48:29 +00001110
Michael Karcherb9dbe482011-05-11 17:07:07 +00001111 switch (spi_programmer->type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +00001112#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001113#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001114 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +00001115 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001116 msg_perr("%s: impossible with this SPI controller,"
Sean Nelson14ba6682010-02-26 05:48:29 +00001117 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001118 return spi_chip_write_1(flash, buf, start, len);
Sean Nelson14ba6682010-02-26 05:48:29 +00001119#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001120#endif
Sean Nelson14ba6682010-02-26 05:48:29 +00001121 default:
1122 break;
1123 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001124
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001125 /* The even start address and even length requirements can be either
1126 * honored outside this function, or we can call spi_byte_program
1127 * for the first and/or last byte and use AAI for the rest.
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001128 * FIXME: Move this to generic code.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001129 */
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001130 /* The data sheet requires a start address with the low bit cleared. */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001131 if (start % 2) {
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001132 msg_cerr("%s: start address not even! Please report a bug at "
1133 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001134 if (spi_chip_write_1(flash, buf, start, start % 2))
1135 return SPI_GENERIC_ERROR;
1136 pos += start % 2;
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001137 cmds[1].writearr = (const unsigned char[]){
1138 JEDEC_AAI_WORD_PROGRAM,
1139 (pos >> 16) & 0xff,
1140 (pos >> 8) & 0xff,
1141 (pos & 0xff),
1142 buf[pos - start],
1143 buf[pos - start + 1]
1144 };
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001145 /* Do not return an error for now. */
1146 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001147 }
1148 /* The data sheet requires total AAI write length to be even. */
1149 if (len % 2) {
1150 msg_cerr("%s: total write length not even! Please report a "
1151 "bug at flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001152 /* Do not return an error for now. */
1153 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001154 }
1155
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001156
1157 result = spi_send_multicommand(cmds);
1158 if (result) {
1159 msg_cerr("%s failed during start command execution\n",
1160 __func__);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001161 /* FIXME: Should we send WRDI here as well to make sure the chip
1162 * is not in AAI mode?
1163 */
Sean Nelson14ba6682010-02-26 05:48:29 +00001164 return result;
Sean Nelson14ba6682010-02-26 05:48:29 +00001165 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001166 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1167 programmer_delay(10);
1168
1169 /* We already wrote 2 bytes in the multicommand step. */
1170 pos += 2;
1171
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001172 /* Are there at least two more bytes to write? */
1173 while (pos < start + len - 1) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001174 cmd[1] = buf[pos++ - start];
1175 cmd[2] = buf[pos++ - start];
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001176 spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
1177 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1178 programmer_delay(10);
1179 }
1180
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001181 /* Use WRDI to exit AAI mode. This needs to be done before issuing any
1182 * other non-AAI command.
1183 */
Sean Nelson14ba6682010-02-26 05:48:29 +00001184 spi_write_disable();
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001185
1186 /* Write remaining byte (if any). */
1187 if (pos < start + len) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001188 if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001189 return SPI_GENERIC_ERROR;
1190 pos += pos % 2;
1191 }
1192
Sean Nelson14ba6682010-02-26 05:48:29 +00001193 return 0;
1194}