blob: 4399377d983b6f9bd901b4e1461a79784ae3fb80 [file] [log] [blame]
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2011 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
21
22#include <stdlib.h>
23#include "flash.h"
24#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000025#include "hwaccess.h"
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000026
27uint8_t *nicintel_bar;
28uint8_t *nicintel_control_bar;
29
30const struct pcidev_status nics_intel[] = {
31 {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +000032 {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000033
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000034 {0},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000035};
36
37/* Arbitrary limit, taken from the datasheet I just had lying around.
38 * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
39 */
40#define NICINTEL_MEMMAP_SIZE (128 * 1024)
41#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
42
David Hendricks8bb20212011-06-14 01:35:36 +000043#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
44
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000045#define CSR_FCR 0x0c
46
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000047static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
48 chipaddr addr);
49static uint8_t nicintel_chip_readb(const struct flashctx *flash,
50 const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000051static const struct par_programmer par_programmer_nicintel = {
52 .chip_readb = nicintel_chip_readb,
53 .chip_readw = fallback_chip_readw,
54 .chip_readl = fallback_chip_readl,
55 .chip_readn = fallback_chip_readn,
56 .chip_writeb = nicintel_chip_writeb,
57 .chip_writew = fallback_chip_writew,
58 .chip_writel = fallback_chip_writel,
59 .chip_writen = fallback_chip_writen,
60};
61
David Hendricks8bb20212011-06-14 01:35:36 +000062static int nicintel_shutdown(void *data)
63{
64 physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
65 physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
66 pci_cleanup(pacc);
David Hendricks8bb20212011-06-14 01:35:36 +000067 return 0;
68}
69
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000070int nicintel_init(void)
71{
72 uintptr_t addr;
73
74 /* Needed only for PCI accesses on some platforms.
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000075 * FIXME: Refactor that into get_mem_perms/rget_io_perms/get_pci_perms?
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000076 */
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000077 if (rget_io_perms())
78 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000079
80 /* No need to check for errors, pcidev_init() will not return in case
81 * of errors.
82 * FIXME: BAR2 is not available if the device uses the CardBus function.
83 */
84 addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);
85
86 nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
87 if (nicintel_bar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +000088 goto error_out_unmap;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000089
90 /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
Carl-Daniel Hailfinger3834c2d2012-07-16 21:32:19 +000091 addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000092 /* FIXME: This is not an aligned mapping. Use 4k? */
David Hendricks8bb20212011-06-14 01:35:36 +000093 nicintel_control_bar = physmap("Intel NIC control/status reg",
94 addr, NICINTEL_CONTROL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000095 if (nicintel_control_bar == ERROR_PTR)
96 goto error_out;
97
David Hendricks8bb20212011-06-14 01:35:36 +000098 if (register_shutdown(nicintel_shutdown, NULL))
99 return 1;
100
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000101 /* FIXME: This register is pretty undocumented in all publicly available
102 * documentation from Intel. Let me quote the complete info we have:
103 * "Flash Control Register: The Flash Control register allows the CPU to
104 * enable writes to an external Flash. The Flash Control Register is a
105 * 32-bit field that allows access to an external Flash device."
106 * Ah yes, we also know where it is, but we have absolutely _no_ idea
107 * what we should do with it. Write 0x0001 because we have nothing
108 * better to do with our time.
109 */
110 pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
111
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000112 max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000113 register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000114
115 return 0;
116
David Hendricks8bb20212011-06-14 01:35:36 +0000117error_out_unmap:
118 physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000119error_out:
120 pci_cleanup(pacc);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000121 return 1;
122}
123
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000124static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
125 chipaddr addr)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000126{
127 pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
128}
129
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000130static uint8_t nicintel_chip_readb(const struct flashctx *flash,
131 const chipaddr addr)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000132{
133 return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
134}