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Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Datasheet:
23 * - Name: Intel 82802AB/82802AC Firmware Hub (FWH)
24 * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm
25 * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf
26 * - Order number: 290658-004
27 */
28
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000029#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "chipdrivers.h"
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000031
32// I need that Berkeley bit-map printer
Sean Nelson28accc22010-03-19 18:47:06 +000033void print_status_82802ab(uint8_t status)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000034{
Sean Nelsoned479d22010-03-24 23:14:32 +000035 msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
36 msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
37 msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
38 msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
39 msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
40 msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
41 msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000042}
43
44int probe_82802ab(struct flashchip *flash)
45{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000046 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000047 uint8_t id1, id2;
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000048 uint8_t flashcontent1, flashcontent2;
Michael Karcherad0010a2010-04-03 10:27:08 +000049 int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000050
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000051 /* Reset to get a clean state */
52 chip_writeb(0xFF, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000053 programmer_delay(10);
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000054
55 /* Enter ID mode */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000056 chip_writeb(0x90, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000057 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000058
Michael Karcherad0010a2010-04-03 10:27:08 +000059 id1 = chip_readb(bios + (0x00 << shifted));
60 id2 = chip_readb(bios + (0x01 << shifted));
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000061
62 /* Leave ID mode */
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000063 chip_writeb(0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000064
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000065 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000066
Sean Nelsoned479d22010-03-24 23:14:32 +000067 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000068
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000069 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +000070 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000071
72 /* Read the product ID location again. We should now see normal flash contents. */
Michael Karcherad0010a2010-04-03 10:27:08 +000073 flashcontent1 = chip_readb(bios + (0x00 << shifted));
74 flashcontent2 = chip_readb(bios + (0x01 << shifted));
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000075
76 if (id1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +000077 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000078 if (id2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +000079 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000080
Sean Nelsoned479d22010-03-24 23:14:32 +000081 msg_cdbg("\n");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000082 if (id1 != flash->manufacture_id || id2 != flash->model_id)
83 return 0;
84
Carl-Daniel Hailfinger81449a22010-03-15 03:48:42 +000085 if (flash->feature_bits & FEATURE_REGISTERMAP)
86 map_flash_registers(flash);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000087
88 return 1;
89}
90
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000091uint8_t wait_82802ab(chipaddr bios)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000092{
93 uint8_t status;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000094
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000095 chip_writeb(0x70, bios);
96 if ((chip_readb(bios) & 0x80) == 0) { // it's busy
97 while ((chip_readb(bios) & 0x80) == 0) ;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000098 }
99
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000100 status = chip_readb(bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000101
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +0000102 /* Reset to get a clean state */
103 chip_writeb(0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000104
105 return status;
106}
107
Sean Nelson28accc22010-03-19 18:47:06 +0000108int unlock_82802ab(struct flashchip *flash)
109{
110 int i;
111 //chipaddr wrprotect = flash->virtual_registers + page + 2;
112
Sean Nelson46313192010-03-20 15:15:36 +0000113 for (i = 0; i < flash->total_size * 1024; i+= flash->page_size)
Sean Nelson28accc22010-03-19 18:47:06 +0000114 {
115 chip_writeb(0, flash->virtual_registers + i + 2);
116 }
117
118 return 0;
119}
120
121int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000122{
Sean Nelson54596372010-01-09 05:30:14 +0000123 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000124 uint8_t status;
125
126 // clear status register
Sean Nelson54596372010-01-09 05:30:14 +0000127 chip_writeb(0x50, bios + page);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000128
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000129 // now start it
Sean Nelson54596372010-01-09 05:30:14 +0000130 chip_writeb(0x20, bios + page);
131 chip_writeb(0xd0, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000132 programmer_delay(10);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000133
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000134 // now let's see what the register is
Sean Nelson54596372010-01-09 05:30:14 +0000135 status = wait_82802ab(bios);
Sean Nelson28accc22010-03-19 18:47:06 +0000136 print_status_82802ab(status);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000137
Sean Nelson54596372010-01-09 05:30:14 +0000138 if (check_erased_range(flash, page, pagesize)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000139 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000140 return -1;
Claus Gindhartef300232008-04-24 09:07:57 +0000141 }
Sean Nelsoned479d22010-03-24 23:14:32 +0000142 msg_cinfo("DONE BLOCK 0x%x\n", page);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000143
144 return 0;
145}
146
147int erase_82802ab(struct flashchip *flash)
148{
149 int i;
150 unsigned int total_size = flash->total_size * 1024;
151
Sean Nelsoned479d22010-03-24 23:14:32 +0000152 msg_cspew("total_size is %d; flash->page_size is %d\n",
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000153 total_size, flash->page_size);
154 for (i = 0; i < total_size; i += flash->page_size)
Sean Nelson28accc22010-03-19 18:47:06 +0000155 if (erase_block_82802ab(flash, i, flash->page_size)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000156 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000157 return -1;
158 }
Sean Nelsoned479d22010-03-24 23:14:32 +0000159 msg_cinfo("DONE ERASE\n");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000160
161 return 0;
162}
163
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000164void write_page_82802ab(chipaddr bios, uint8_t *src,
165 chipaddr dst, int page_size)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000166{
167 int i;
168
169 for (i = 0; i < page_size; i++) {
170 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000171 chip_writeb(0x40, dst);
172 chip_writeb(*src++, dst++);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000173 wait_82802ab(bios);
174 }
175}
176
177int write_82802ab(struct flashchip *flash, uint8_t *buf)
178{
179 int i;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000180 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000181
Michael Karcherad0010a2010-04-03 10:27:08 +0000182 if (erase_flash(flash)) {
183 msg_cerr("ERASE FAILED!\n");
184 return -1;
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000185 }
Claus Gindhartef300232008-04-24 09:07:57 +0000186
Michael Karcherad0010a2010-04-03 10:27:08 +0000187 msg_cinfo("Programming at: ");
188 for (i = 0; i < flash->total_size; i++) {
189 if ((i & 0x3) == 0)
190 msg_cinfo("address: 0x%08lx", (unsigned long)i * 1024);
Claus Gindhartef300232008-04-24 09:07:57 +0000191
Michael Karcherad0010a2010-04-03 10:27:08 +0000192 write_page_82802ab(bios, buf + i * 1024, bios + i * 1024, 1024);
193
194 if ((i & 0x3) == 0)
195 msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000196 }
Michael Karcherad0010a2010-04-03 10:27:08 +0000197
Sean Nelsoned479d22010-03-24 23:14:32 +0000198 msg_cinfo("DONE!\n");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000199 return 0;
200}
Sean Nelsondee4a832010-03-22 04:39:31 +0000201
Sean Nelson88647102010-03-22 06:57:02 +0000202int unlock_28f004s5(struct flashchip *flash)
Sean Nelsondee4a832010-03-22 04:39:31 +0000203{
204 chipaddr bios = flash->virtual_memory;
Sean Nelson4e54de92010-03-22 07:03:26 +0000205 uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0;
206 int i;
Sean Nelsondee4a832010-03-22 04:39:31 +0000207
208 /* Clear status register */
209 chip_writeb(0x50, bios);
210
211 /* Read identifier codes */
212 chip_writeb(0x90, bios);
213
214 /* Read master lock-bit */
215 mcfg = chip_readb(bios + 0x3);
Sean Nelsoned479d22010-03-24 23:14:32 +0000216 msg_cdbg("master lock is ");
Sean Nelsondee4a832010-03-22 04:39:31 +0000217 if (mcfg) {
218 msg_cdbg("locked!\n");
219 } else {
220 msg_cdbg("unlocked!\n");
221 can_unlock = 1;
222 }
223
224 /* Read block lock-bits */
225 for (i = 0; i < flash->total_size * 1024; i+= (64 * 1024)) {
226 bcfg = chip_readb(bios + i + 2); // read block lock config
227 msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un");
228 if (bcfg) {
229 need_unlock = 1;
230 }
231 }
232
233 /* Reset chip */
234 chip_writeb(0xFF, bios);
235
236 /* Unlock: clear block lock-bits, if needed */
237 if (can_unlock && need_unlock) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000238 msg_cdbg("Unlock: ");
Sean Nelsondee4a832010-03-22 04:39:31 +0000239 chip_writeb(0x60, bios);
240 chip_writeb(0xD0, bios);
241 chip_writeb(0xFF, bios);
Sean Nelsoned479d22010-03-24 23:14:32 +0000242 msg_cdbg("Done!\n");
Sean Nelsondee4a832010-03-22 04:39:31 +0000243 }
244
245 /* Error: master locked or a block is locked */
246 if (!can_unlock && need_unlock) {
247 msg_cerr("At least one block is locked and lockdown is active!\n");
248 return -1;
249 }
250
251 return 0;
252}