Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Felix Singer | 980d6b8 | 2022-08-19 02:48:15 +0200 | [diff] [blame] | 17 | #include <stdbool.h> |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 18 | #include <stdlib.h> |
| 19 | #include <string.h> |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 20 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 21 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 22 | #include "hwaccess.h" |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 23 | |
| 24 | #define PCI_VENDOR_ID_NVIDIA 0x10de |
| 25 | |
Carl-Daniel Hailfinger | fb2c4c3 | 2010-07-17 22:42:33 +0000 | [diff] [blame] | 26 | /* Mask to restrict flash accesses to a 128kB memory window. |
| 27 | * FIXME: Is this size a one-fits-all or card dependent? |
| 28 | */ |
| 29 | #define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1) |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 30 | #define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024) |
Carl-Daniel Hailfinger | fb2c4c3 | 2010-07-17 22:42:33 +0000 | [diff] [blame] | 31 | |
Jacob Garber | afc3ad6 | 2019-06-24 16:05:28 -0600 | [diff] [blame] | 32 | static uint8_t *nvidia_bar; |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 33 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 34 | static const struct dev_entry gfx_nvidia[] = { |
Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 35 | {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, |
| 36 | {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, |
| 37 | {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, |
| 38 | {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, |
| 39 | {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" }, |
| 40 | {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" }, |
| 41 | {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, |
| 42 | {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" }, |
| 43 | {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" }, |
| 44 | {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" }, |
| 45 | {0x10de, 0x0103, NT, "NVIDIA", "Quadro" }, |
| 46 | {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" }, |
| 47 | {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" }, |
| 48 | {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" }, |
| 49 | {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" }, |
| 50 | {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" }, |
| 51 | {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" }, |
| 52 | {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" }, |
| 53 | {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" }, |
| 54 | {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" }, |
| 55 | {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" }, |
| 56 | {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" }, |
| 57 | {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" }, |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 58 | |
Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 59 | {0}, |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 60 | }; |
| 61 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 62 | static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 63 | chipaddr addr); |
| 64 | static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, |
| 65 | const chipaddr addr); |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 66 | static const struct par_master par_master_gfxnvidia = { |
Felix Singer | dd547c7 | 2021-10-13 13:56:38 +0200 | [diff] [blame] | 67 | .chip_readb = gfxnvidia_chip_readb, |
| 68 | .chip_readw = fallback_chip_readw, |
| 69 | .chip_readl = fallback_chip_readl, |
| 70 | .chip_readn = fallback_chip_readn, |
| 71 | .chip_writeb = gfxnvidia_chip_writeb, |
| 72 | .chip_writew = fallback_chip_writew, |
| 73 | .chip_writel = fallback_chip_writel, |
| 74 | .chip_writen = fallback_chip_writen, |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 75 | }; |
| 76 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 77 | static int gfxnvidia_init(void) |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 78 | { |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 79 | struct pci_dev *dev = NULL; |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 80 | uint32_t reg32; |
| 81 | |
Carl-Daniel Hailfinger | d6bb828 | 2012-07-21 17:27:08 +0000 | [diff] [blame] | 82 | if (rget_io_perms()) |
| 83 | return 1; |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 84 | |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 85 | dev = pcidev_init(gfx_nvidia, PCI_BASE_ADDRESS_0); |
| 86 | if (!dev) |
| 87 | return 1; |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 88 | |
Stefan Tauner | 0ccec8f | 2014-06-01 23:49:03 +0000 | [diff] [blame] | 89 | uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); |
Niklas Söderlund | 89edf36 | 2013-08-23 23:29:23 +0000 | [diff] [blame] | 90 | if (!io_base_addr) |
| 91 | return 1; |
| 92 | |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 93 | io_base_addr += 0x300000; |
Sean Nelson | 8e5e73e | 2010-01-09 23:54:05 +0000 | [diff] [blame] | 94 | msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 95 | |
Stefan Tauner | 7fb5aa0 | 2013-08-14 15:48:44 +0000 | [diff] [blame] | 96 | nvidia_bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); |
| 97 | if (nvidia_bar == ERROR_PTR) |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 98 | return 1; |
| 99 | |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 100 | /* Allow access to flash interface (will disable screen). */ |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 101 | reg32 = pci_read_long(dev, 0x50); |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 102 | reg32 &= ~(1 << 0); |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 103 | rpci_write_long(dev, 0x50, reg32); |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 104 | |
Carl-Daniel Hailfinger | bf3af29 | 2010-07-29 14:41:46 +0000 | [diff] [blame] | 105 | /* Write/erase doesn't work. */ |
Felix Singer | 980d6b8 | 2022-08-19 02:48:15 +0200 | [diff] [blame] | 106 | programmer_may_write = false; |
Anastasia Klimchuk | b91a203 | 2021-05-21 09:40:58 +1000 | [diff] [blame] | 107 | register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, NULL); |
Carl-Daniel Hailfinger | bf3af29 | 2010-07-29 14:41:46 +0000 | [diff] [blame] | 108 | |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 109 | return 0; |
| 110 | } |
| 111 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 112 | static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 113 | chipaddr addr) |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 114 | { |
Carl-Daniel Hailfinger | 1d3a2fe | 2010-07-27 22:03:46 +0000 | [diff] [blame] | 115 | pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 118 | static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, |
| 119 | const chipaddr addr) |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 120 | { |
Carl-Daniel Hailfinger | 1d3a2fe | 2010-07-27 22:03:46 +0000 | [diff] [blame] | 121 | return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); |
Uwe Hermann | 2bc98f6 | 2009-09-30 18:29:55 +0000 | [diff] [blame] | 122 | } |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 123 | |
| 124 | const struct programmer_entry programmer_gfxnvidia = { |
| 125 | .name = "gfxnvidia", |
| 126 | .type = PCI, |
| 127 | .devs.dev = gfx_nvidia, |
| 128 | .init = gfxnvidia_init, |
| 129 | .map_flash_region = fallback_map, |
| 130 | .unmap_flash_region = fallback_unmap, |
| 131 | .delay = internal_delay, |
| 132 | }; |