blob: b55625e06e43c8d95ecfe0b371be11f492859ee5 [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#if defined(__i386__) || defined(__x86_64__)
23
24#include "ich_descriptors.h"
Stefan Taunerb3850962011-12-24 00:00:32 +000025
26#ifdef ICH_DESCRIPTORS_FROM_DUMP
27
28#include <stdio.h>
29#define print(t, ...) printf(__VA_ARGS__)
30#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a
31/* The upper map is located in the word before the 256B-long OEM section at the
32 * end of the 4kB-long flash descriptor.
33 */
34#define UPPER_MAP_OFFSET (4096 - 256 - 4)
35#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0)
36
37#else /* ICH_DESCRIPTORS_FROM_DUMP */
38
Stefan Tauner1e146392011-09-15 23:52:55 +000039#include "flash.h" /* for msg_* */
40#include "programmer.h"
41
Stefan Taunerb3850962011-12-24 00:00:32 +000042#endif /* ICH_DESCRIPTORS_FROM_DUMP */
43
44#ifndef min
45#define min(a, b) (a < b) ? a : b
46#endif
47
Stefan Tauner1e146392011-09-15 23:52:55 +000048void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity)
49{
50 print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
51 print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
52 print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
53 print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
54 print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
55 print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
56}
57
58#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0)
59#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0)
60#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0)
61#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0)
62#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0)
63
64void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc)
65{
66 prettyprint_ich_descriptor_content(&desc->content);
67 prettyprint_ich_descriptor_component(desc);
68 prettyprint_ich_descriptor_region(desc);
69 prettyprint_ich_descriptor_master(&desc->master);
Stefan Taunerb3850962011-12-24 00:00:32 +000070#ifdef ICH_DESCRIPTORS_FROM_DUMP
71 if (cs >= CHIPSET_ICH8) {
72 prettyprint_ich_descriptor_upper_map(&desc->upper);
73 prettyprint_ich_descriptor_straps(cs, desc);
74 }
75#endif /* ICH_DESCRIPTORS_FROM_DUMP */
Stefan Tauner1e146392011-09-15 23:52:55 +000076}
77
78void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont)
79{
80 msg_pdbg2("=== Content Section ===\n");
81 msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG);
82 msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0);
83 msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1);
84 msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2);
85 msg_pdbg2("\n");
86
87 msg_pdbg2("--- Details ---\n");
88 msg_pdbg2("NR (Number of Regions): %5d\n",
89 cont->NR + 1);
90 msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n",
91 getFRBA(cont));
92 msg_pdbg2("NC (Number of Components): %5d\n",
93 cont->NC + 1);
94 msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n",
95 getFCBA(cont));
96 msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n",
97 cont->ISL);
98 msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n",
99 getFISBA(cont));
100 msg_pdbg2("NM (Number of Masters): %5d\n",
101 cont->NM + 1);
102 msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n",
103 getFMBA(cont));
104 msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n",
105 cont->MSL);
106 msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n",
107 getFMSBA(cont));
108 msg_pdbg2("\n");
109}
110
111void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc)
112{
113 static const char * const freq_str[8] = {
114 "20 MHz", /* 000 */
115 "33 MHz", /* 001 */
116 "reserved", /* 010 */
117 "reserved", /* 011 */
118 "50 MHz", /* 100 */
119 "reserved", /* 101 */
120 "reserved", /* 110 */
121 "reserved" /* 111 */
122 };
123 static const char * const size_str[8] = {
124 "512 kB", /* 000 */
125 " 1 MB", /* 001 */
126 " 2 MB", /* 010 */
127 " 4 MB", /* 011 */
128 " 8 MB", /* 100 */
129 " 16 MB", /* 101 */
130 "reserved", /* 110 */
131 "reserved", /* 111 */
132 };
133
134 msg_pdbg2("=== Component Section ===\n");
135 msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP);
136 msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL );
137 msg_pdbg2("\n");
138
139 msg_pdbg2("--- Details ---\n");
140 msg_pdbg2("Component 1 density: %s\n",
141 size_str[desc->component.comp1_density]);
142 if (desc->content.NC)
143 msg_pdbg2("Component 2 density: %s\n",
144 size_str[desc->component.comp2_density]);
145 else
146 msg_pdbg2("Component 2 is not used.\n");
147 msg_pdbg2("Read Clock Frequency: %s\n",
148 freq_str[desc->component.freq_read]);
149 msg_pdbg2("Read ID and Status Clock Freq.: %s\n",
150 freq_str[desc->component.freq_read_id]);
151 msg_pdbg2("Write and Erase Clock Freq.: %s\n",
152 freq_str[desc->component.freq_write]);
153 msg_pdbg2("Fast Read is %ssupported.\n",
154 desc->component.fastread ? "" : "not ");
155 if (desc->component.fastread)
156 msg_pdbg2("Fast Read Clock Frequency: %s\n",
157 freq_str[desc->component.freq_fastread]);
158 if (desc->component.FLILL == 0)
159 msg_pdbg2("No forbidden opcodes.\n");
160 else {
161 msg_pdbg2("Invalid instruction 0: 0x%02x\n",
162 desc->component.invalid_instr0);
163 msg_pdbg2("Invalid instruction 1: 0x%02x\n",
164 desc->component.invalid_instr1);
165 msg_pdbg2("Invalid instruction 2: 0x%02x\n",
166 desc->component.invalid_instr2);
167 msg_pdbg2("Invalid instruction 3: 0x%02x\n",
168 desc->component.invalid_instr3);
169 }
170 msg_pdbg2("\n");
171}
172
173static void pprint_freg(const struct ich_desc_region *reg, uint32_t i)
174{
175 static const char *const region_names[5] = {
176 "Descr.", "BIOS", "ME", "GbE", "Platf."
177 };
178 if (i >= 5) {
179 msg_pdbg2("%s: region index too high.\n", __func__);
180 return;
181 }
182 uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]);
183 uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]);
184 msg_pdbg2("Region %d (%-6s) ", i, region_names[i]);
185 if (base > limit)
186 msg_pdbg2("is unused.\n");
187 else
188 msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff);
189}
190
191void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc)
192{
193 uint8_t i;
194 uint8_t nr = desc->content.NR + 1;
195 msg_pdbg2("=== Region Section ===\n");
Stefan Tauner2abab942012-04-27 20:41:23 +0000196 if (nr > 5) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000197 msg_pdbg2("%s: number of regions too high (%d).\n", __func__,
198 nr);
199 return;
200 }
201 for (i = 0; i <= nr; i++)
202 msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]);
203 msg_pdbg2("\n");
204
205 msg_pdbg2("--- Details ---\n");
206 for (i = 0; i <= nr; i++)
207 pprint_freg(&desc->region, i);
208 msg_pdbg2("\n");
209}
210
211void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr)
212{
213 msg_pdbg2("=== Master Section ===\n");
214 msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1);
215 msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2);
216 msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3);
217 msg_pdbg2("\n");
218
219 msg_pdbg2("--- Details ---\n");
220 msg_pdbg2(" Descr. BIOS ME GbE Platf.\n");
221 msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n",
222 (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ',
223 (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ',
224 (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ',
225 (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ',
226 (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' ');
227 msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n",
228 (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ',
229 (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ',
230 (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ',
231 (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ',
232 (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' ');
233 msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n",
234 (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ',
235 (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ',
236 (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ',
237 (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ',
238 (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' ');
239 msg_pdbg2("\n");
240}
241
Stefan Taunerb3850962011-12-24 00:00:32 +0000242#ifdef ICH_DESCRIPTORS_FROM_DUMP
243
244void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc)
245{
246 static const char * const str_GPIO12[4] = {
247 "GPIO12",
248 "LAN PHY Power Control Function (Native Output)",
249 "GLAN_DOCK# (Native Input)",
250 "invalid configuration",
251 };
252
253 msg_pdbg2("--- MCH details ---\n");
254 msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en");
255 msg_pdbg2("\n");
256
257 msg_pdbg2("--- ICH details ---\n");
258 msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD);
259 msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2);
260 msg_pdbg2("ME SMBus Controller is connected to the %s.\n",
261 desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins");
262 msg_pdbg2("SPI CS1 is used for %s.\n",
263 desc->south.ich8.SPICS1_LANPHYPC_SEL ?
264 "LAN PHY Power Control Function" :
265 "SPI Chip Select");
266 msg_pdbg2("GPIO12 is used as %s.\n",
267 str_GPIO12[desc->south.ich8.GPIO12_SEL]);
268 msg_pdbg2("PCIe Port 6 is used for %s.\n",
269 desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express");
270 msg_pdbg2("%sn BMC Mode: "
271 "Intel AMT SMBus Controller 1 is connected to %s.\n",
272 desc->south.ich8.BMCMODE ? "I" : "Not i",
273 desc->south.ich8.BMCMODE ? "SMLink" : "SMBus");
274 msg_pdbg2("TCO is in %s Mode.\n",
275 desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible");
276 msg_pdbg2("ME A is %sabled.\n",
277 desc->south.ich8.ME_DISABLE ? "dis" : "en");
278 msg_pdbg2("\n");
279}
280
281static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t off)
282{
283 msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1);
284
285 off *= 4;
286 switch(conf){
287 case 0:
288 msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off);
289 break;
290 case 1:
291 msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), "
292 "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off);
293 break;
294 case 2:
295 msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports "
296 "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off);
297 break;
298 case 3:
299 msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)",
300 1+off, 2+off, 4+off);
301 break;
302 }
303 msg_pdbg2("\n");
304}
305
306void prettyprint_ich_descriptor_pchstraps45678_56(const struct ich_desc_south_strap *s)
307{
308 /* PCHSTRP4 */
309 msg_pdbg2("Intel PHY is %s.\n",
310 (s->ibex.PHYCON == 2) ? "connected" :
311 (s->ibex.PHYCON == 0) ? "disconnected" : "reserved");
312 msg_pdbg2("GbE MAC SMBus address is %sabled.\n",
313 s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis");
314 msg_pdbg2("GbE MAC SMBus address: 0x%02x\n",
315 s->ibex.GBEMAC_SMBUS_ADDR);
316 msg_pdbg2("GbE PHY SMBus address: 0x%02x\n",
317 s->ibex.GBEPHY_SMBUS_ADDR);
318
319 /* PCHSTRP5 */
320 /* PCHSTRP6 */
321 /* PCHSTRP7 */
322 msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n",
323 s->ibex.MESMA2UDID_VENDOR);
324 msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n",
325 s->ibex.MESMA2UDID_VENDOR);
326
327 /* PCHSTRP8 */
328}
329
330void prettyprint_ich_descriptor_pchstraps111213_56(const struct ich_desc_south_strap *s)
331{
332 /* PCHSTRP11 */
333 msg_pdbg2("SMLink1 GP Address is %sabled.\n",
334 s->ibex.SML1GPAEN ? "en" : "dis");
335 msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n",
336 s->ibex.SML1GPA);
337 msg_pdbg2("SMLink1 I2C Target address is %sabled.\n",
338 s->ibex.SML1I2CAEN ? "en" : "dis");
339 msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n",
340 s->ibex.SML1I2CA);
341
342 /* PCHSTRP12 */
343 /* PCHSTRP13 */
344}
345
346void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s)
347{
348 static const uint8_t const dec_t209min[4] = {
349 100,
350 50,
351 5,
352 1
353 };
354
355 msg_pdbg2("--- PCH ---\n");
356
357 /* PCHSTRP0 */
358 msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2);
359 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
360 s->ibex.SMB_EN ? "en" : "dis");
361 msg_pdbg2("SMLink0 segment is %sabled.\n",
362 s->ibex.SML0_EN ? "en" : "dis");
363 msg_pdbg2("SMLink1 segment is %sabled.\n",
364 s->ibex.SML1_EN ? "en" : "dis");
365 msg_pdbg2("SMLink1 Frequency: %s\n",
366 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
367 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
368 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
369 msg_pdbg2("SMLink0 Frequency: %s\n",
370 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
371 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
372 "LAN_PHY_PWR_CTRL" : "general purpose output");
373 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->ibex.cs_ss1);
374 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
375 s->ibex.DMI_REQID_DIS ? "en" : "dis");
376 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
377 1 << (6 + s->ibex.BBBS));
378
379 /* PCHSTRP1 */
380 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
381
382 /* PCHSTRP2 */
383 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
384 s->ibex.MESMASDEN ? "en" : "dis");
385 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
386 s->ibex.MESMASDA);
387 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
388 s->ibex.MESMI2CEN ? "en" : "dis");
389 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
390 s->ibex.MESMI2CA);
391
392 /* PCHSTRP3 */
393 prettyprint_ich_descriptor_pchstraps45678_56(s);
394 /* PCHSTRP9 */
395 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
396 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
397 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
398 s->ibex.PCIELR1 ? "" : "not ");
399 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
400 s->ibex.PCIELR2 ? "" : "not ");
401 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
402 s->ibex.DMILR ? "" : "not ");
403 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
404 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
405 s->ibex.PHY_PCIE_EN ? "en" : "dis");
406
407 /* PCHSTRP10 */
408 msg_pdbg2("Management Engine will boot from %sflash.\n",
409 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
410 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5);
411 msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n",
412 s->ibex.VE_EN ? "en" : "dis");
413 msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n",
414 s->ibex.MMDDE ? "en" : "dis");
415 msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n",
416 s->ibex.MMADDR);
417 msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7);
418 msg_pdbg2("Integrated Clocking Configuration is %d.\n",
419 (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL);
420 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a "
421 "reset.\n", s->ibex.MER_CL1 ? "" : "not ");
422
423 prettyprint_ich_descriptor_pchstraps111213_56(s);
424
425 /* PCHSTRP14 */
426 msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n",
427 s->ibex.VE_EN2 ? "en" : "dis");
428 msg_pdbg2("Virtualization Engine will boot from %sflash.\n",
429 s->ibex.VE_BOOT_FLASH ? "" : "ROM, then ");
430 msg_pdbg2("Braidwood SSD functionality is %sabled.\n",
431 s->ibex.BW_SSD ? "en" : "dis");
432 msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n",
433 s->ibex.NVMHCI_EN ? "en" : "dis");
434
435 /* PCHSTRP15 */
436 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6);
437 msg_pdbg2("Integrated wired LAN Solution is %sabled.\n",
438 s->ibex.IWL_EN ? "en" : "dis");
439 msg_pdbg2("t209 min Timing: %d ms\n",
440 dec_t209min[s->ibex.t209min]);
441 msg_pdbg2("\n");
442}
443
444void prettyprint_ich_descriptor_straps_cougar(const struct ich_desc_south_strap *s)
445{
446 msg_pdbg2("--- PCH ---\n");
447
448 /* PCHSTRP0 */
449 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->cougar.cs_ss1);
450 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
451 s->ibex.SMB_EN ? "en" : "dis");
452 msg_pdbg2("SMLink0 segment is %sabled.\n",
453 s->ibex.SML0_EN ? "en" : "dis");
454 msg_pdbg2("SMLink1 segment is %sabled.\n",
455 s->ibex.SML1_EN ? "en" : "dis");
456 msg_pdbg2("SMLink1 Frequency: %s\n",
457 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
458 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
459 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
460 msg_pdbg2("SMLink0 Frequency: %s\n",
461 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
462 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
463 "LAN_PHY_PWR_CTRL" : "general purpose output");
464 msg_pdbg2("LinkSec is %sabled.\n",
465 s->cougar.LINKSEC_DIS ? "en" : "dis");
466 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
467 s->ibex.DMI_REQID_DIS ? "en" : "dis");
468 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
469 1 << (6 + s->ibex.BBBS));
470
471 /* PCHSTRP1 */
472 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
473 msg_pdbg2("Chipset configuration Softstrap 2: 0x%x\n", s->ibex.cs_ss2);
474
475 /* PCHSTRP2 */
476 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
477 s->ibex.MESMASDEN ? "en" : "dis");
478 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
479 s->ibex.MESMASDA);
480 msg_pdbg2("ME SMBus MCTP Address is %sabled.\n",
481 s->cougar.MESMMCTPAEN ? "en" : "dis");
482 msg_pdbg2("ME SMBus MCTP target address: 0x%02x\n",
483 s->cougar.MESMMCTPA);
484 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
485 s->ibex.MESMI2CEN ? "en" : "dis");
486 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
487 s->ibex.MESMI2CA);
488
489 /* PCHSTRP3 */
490 prettyprint_ich_descriptor_pchstraps45678_56(s);
491 /* PCHSTRP9 */
492 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
493 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
494 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
495 s->ibex.PCIELR1 ? "" : "not ");
496 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
497 s->ibex.PCIELR2 ? "" : "not ");
498 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
499 s->ibex.DMILR ? "" : "not ");
500 msg_pdbg2("ME Debug status writes over SMBUS are %sabled.\n",
501 s->cougar.MDSMBE_EN ? "en" : "dis");
502 msg_pdbg2("ME Debug SMBus Emergency Mode address: 0x%02x (raw)\n",
503 s->cougar.MDSMBE_ADD);
504 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
505 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
506 s->ibex.PHY_PCIE_EN ? "en" : "dis");
507 msg_pdbg2("PCIe ports Subtractive Decode Agent is %sabled.\n",
508 s->cougar.SUB_DECODE_EN ? "en" : "dis");
509 msg_pdbg2("GPIO74 is used as %s.\n", s->cougar.PCHHOT_SML1ALERT_SEL ?
510 "PCHHOT#" : "SML1ALERT#");
511
512 /* PCHSTRP10 */
513 msg_pdbg2("Management Engine will boot from %sflash.\n",
514 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
515
516 msg_pdbg2("ME Debug SMBus Emergency Mode is %sabled.\n",
517 s->cougar.MDSMBE_EN ? "en" : "dis");
518 msg_pdbg2("ME Debug SMBus Emergency Mode Address: 0x%02x\n",
519 s->cougar.MDSMBE_ADD);
520
521 msg_pdbg2("Integrated Clocking Configuration used: %d\n",
522 s->cougar.ICC_SEL);
523 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a "
524 "reset.\n", s->ibex.MER_CL1 ? "" : "not ");
525 msg_pdbg2("ICC Profile is selected by %s.\n",
526 s->cougar.ICC_PRO_SEL ? "Softstraps" : "BIOS");
527 msg_pdbg2("Deep SX is %ssupported on the platform.\n",
528 s->cougar.Deep_SX_EN ? "not " : "");
529 msg_pdbg2("ME Debug LAN Emergency Mode is %sabled.\n",
530 s->cougar.ME_DBG_LAN ? "en" : "dis");
531
532 prettyprint_ich_descriptor_pchstraps111213_56(s);
533
534 /* PCHSTRP14 */
535 /* PCHSTRP15 */
536 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->cougar.cs_ss6);
537 msg_pdbg2("Integrated wired LAN is %sabled.\n",
538 s->cougar.IWL_EN ? "en" : "dis");
539 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->cougar.cs_ss5);
540 msg_pdbg2("SMLink1 provides temperature from %s.\n",
541 s->cougar.SMLINK1_THERM_SEL ?
542 "PCH only" : "the CPU, PCH and DIMMs");
543 msg_pdbg2("GPIO29 is used as %s.\n", s->cougar.SLP_LAN_GP29_SEL ?
544 "general purpose output" : "SLP_LAN#");
545
546 /* PCHSTRP16 */
547 /* PCHSTRP17 */
548 msg_pdbg2("Integrated Clock: %s Clock Mode\n",
549 s->cougar.ICML ? "Buffered Through" : "Full Integrated");
550 msg_pdbg2("\n");
551}
552
553void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc)
554{
555 unsigned int i, max;
556 msg_pdbg2("=== Softstraps ===\n");
557
558 if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) {
559 max = sizeof(desc->north.STRPs) / 4 + 1;
560 msg_pdbg2("MSL (%u) is greater than the current maximum of %u "
561 "entries.\n", desc->content.MSL, max + 1);
562 msg_pdbg2("Only the first %u entries will be printed.\n", max);
563 } else
564 max = desc->content.MSL;
565
566 msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max);
567 for (i = 0; i < max; i++)
568 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]);
569 msg_pdbg2("\n");
570
571 if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) {
572 max = sizeof(desc->south.STRPs) / 4;
573 msg_pdbg2("ISL (%u) is greater than the current maximum of %u "
574 "entries.\n", desc->content.ISL, max);
575 msg_pdbg2("Only the first %u entries will be printed.\n", max);
576 } else
577 max = desc->content.ISL;
578
579 msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max);
580 for (i = 0; i < max; i++)
581 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]);
582 msg_pdbg2("\n");
583
584 switch (cs) {
585 case CHIPSET_ICH8:
586 if (sizeof(desc->north.ich8) / 4 != desc->content.MSL)
587 msg_pdbg2("Detailed North/MCH/PROC information is "
588 "probably not reliable, printing anyway.\n");
589 if (sizeof(desc->south.ich8) / 4 != desc->content.ISL)
590 msg_pdbg2("Detailed South/ICH/PCH information is "
591 "probably not reliable, printing anyway.\n");
592 prettyprint_ich_descriptor_straps_ich8(desc);
593 break;
594 case CHIPSET_5_SERIES_IBEX_PEAK:
595 /* PCH straps only. PROCSTRPs are unknown. */
596 if (sizeof(desc->south.ibex) / 4 != desc->content.ISL)
597 msg_pdbg2("Detailed South/ICH/PCH information is "
598 "probably not reliable, printing anyway.\n");
599 prettyprint_ich_descriptor_straps_ibex(&desc->south);
600 break;
601 case CHIPSET_6_SERIES_COUGAR_POINT:
602 /* PCH straps only. PROCSTRP0 is "reserved". */
603 if (sizeof(desc->south.cougar) / 4 != desc->content.ISL)
604 msg_pdbg2("Detailed South/ICH/PCH information is "
605 "probably not reliable, printing anyway.\n");
606 prettyprint_ich_descriptor_straps_cougar(&desc->south);
607 break;
608 case CHIPSET_ICH_UNKNOWN:
609 break;
610 default:
611 msg_pdbg2("The meaning of the descriptor straps are unknown "
612 "yet.\n\n");
613 break;
614 }
615}
616
617void prettyprint_rdid(uint32_t reg_val)
618{
619 uint8_t mid = reg_val & 0xFF;
620 uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00);
621 msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did);
622}
623
624void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap)
625{
626 int i;
627 msg_pdbg2("=== Upper Map Section ===\n");
628 msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1);
629 msg_pdbg2("\n");
630
631 msg_pdbg2("--- Details ---\n");
632 msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL);
633 msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap));
634 msg_pdbg2("\n");
635
636 msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2);
637 for (i = 0; i < umap->VTL/2; i++)
638 {
639 uint32_t jid = umap->vscc_table[i].JID;
640 uint32_t vscc = umap->vscc_table[i].VSCC;
641 msg_pdbg2(" JID%d = 0x%08x\n", i, jid);
642 msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc);
643 msg_pdbg2(" "); /* indention */
644 prettyprint_rdid(jid);
645 msg_pdbg2(" "); /* indention */
646 prettyprint_ich_reg_vscc(vscc, 0);
647 }
648 msg_pdbg2("\n");
649}
650
651/* len is the length of dump in bytes */
652int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc)
653{
654 unsigned int i, max;
655 uint8_t pch_bug_offset = 0;
656
657 if (dump == NULL || desc == NULL)
658 return ICH_RET_PARAM;
659
660 if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) {
661 if (dump[4] == DESCRIPTOR_MODE_SIGNATURE)
662 pch_bug_offset = 4;
663 else
664 return ICH_RET_ERR;
665 }
666
667 /* map */
668 if (len < (4 + pch_bug_offset) * 4 - 1)
669 return ICH_RET_OOB;
670 desc->content.FLVALSIG = dump[0 + pch_bug_offset];
671 desc->content.FLMAP0 = dump[1 + pch_bug_offset];
672 desc->content.FLMAP1 = dump[2 + pch_bug_offset];
673 desc->content.FLMAP2 = dump[3 + pch_bug_offset];
674
675 /* component */
676 if (len < (getFCBA(&desc->content) + 3 * 4 - 1))
677 return ICH_RET_OOB;
678 desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0];
679 desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1];
680 desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2];
681
682 /* region */
683 if (len < (getFRBA(&desc->content) + 5 * 4 - 1))
684 return ICH_RET_OOB;
685 desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0];
686 desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1];
687 desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2];
688 desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3];
689 desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4];
690
691 /* master */
692 if (len < (getFMBA(&desc->content) + 3 * 4 - 1))
693 return ICH_RET_OOB;
694 desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0];
695 desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1];
696 desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2];
697
698 /* upper map */
699 desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0];
700
701 /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide:
702 * "Identifies the 1s based number of DWORDS contained in the VSCC
703 * Table. Each SPI component entry in the table is 2 DWORDS long." So
704 * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A
705 * check ensures that the maximum offset actually accessed is available.
706 */
707 if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1))
708 return ICH_RET_OOB;
709
710 for (i = 0; i < desc->upper.VTL/2; i++) {
711 desc->upper.vscc_table[i].JID =
712 dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0];
713 desc->upper.vscc_table[i].VSCC =
714 dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1];
715 }
716
717 /* MCH/PROC (aka. North) straps */
718 if (len < getFMSBA(&desc->content) + desc->content.MSL * 4)
719 return ICH_RET_OOB;
720
721 /* limit the range to be written */
722 max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL);
723 for (i = 0; i < max; i++)
724 desc->north.STRPs[i] =
725 dump[(getFMSBA(&desc->content) >> 2) + i];
726
727 /* ICH/PCH (aka. South) straps */
728 if (len < getFISBA(&desc->content) + desc->content.ISL * 4)
729 return ICH_RET_OOB;
730
731 /* limit the range to be written */
732 max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL);
733 for (i = 0; i < max; i++)
734 desc->south.STRPs[i] =
735 dump[(getFISBA(&desc->content) >> 2) + i];
736
737 return ICH_RET_OK;
738}
739
740#else /* ICH_DESCRIPTORS_FROM_DUMP */
741
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000742/** Returns the integer representation of the component density with index
743idx in bytes or 0 if a correct size can not be determined. */
744int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx)
745{
746 uint8_t size_enc;
747
748 switch(idx) {
749 case 0:
750 size_enc = desc->component.comp1_density;
751 break;
752 case 1:
753 if (desc->content.NC == 0)
754 return 0;
755 size_enc = desc->component.comp2_density;
756 break;
757 default:
758 msg_perr("Only ICH SPI component index 0 or 1 are supported "
759 "yet.\n");
760 return 0;
761 }
762 if (size_enc > 5) {
763 msg_perr("Density of ICH SPI component with index %d is "
764 "invalid. Encoded density is 0x%x.\n", idx, size_enc);
765 return 0;
766 }
767 return (1 << (19 + size_enc));
768}
769
Stefan Tauner1e146392011-09-15 23:52:55 +0000770static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar)
771{
772 uint32_t control = 0;
773 control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS;
774 control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI;
775 mmio_le_writel(control, spibar + ICH9_REG_FDOC);
776 return mmio_le_readl(spibar + ICH9_REG_FDOD);
777}
778
779int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
780{
781 uint8_t i;
782 uint8_t nr;
783 struct ich_desc_region *r = &desc->region;
784
785 /* Test if bit-fields are working as expected.
786 * FIXME: Replace this with dynamic bitfield fixup
787 */
788 for (i = 0; i < 4; i++)
789 desc->region.FLREGs[i] = 0x5A << (i * 8);
790 if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 ||
791 r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 ||
792 r->reg2_base != 0x0000 || r->reg2_limit != 0x005A ||
793 r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) {
794 msg_pdbg("The combination of compiler and CPU architecture used"
795 "does not lay out bit-fields as expected, sorry.\n");
796 msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base);
797 msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit);
798 msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base);
799 msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit);
800 msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base);
801 msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit);
802 msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base);
803 msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit);
804 return ICH_RET_ERR;
805 }
806
807 msg_pdbg2("Reading flash descriptors "
808 "mapped by the chipset via FDOC/FDOD...");
809 /* content section */
810 desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar);
811 desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar);
812 desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar);
813 desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar);
814
815 /* component section */
816 desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar);
817 desc->component.FLILL = read_descriptor_reg(1, 1, spibar);
818 desc->component.FLPB = read_descriptor_reg(1, 2, spibar);
819
820 /* region section */
821 nr = desc->content.NR + 1;
Stefan Tauner2abab942012-04-27 20:41:23 +0000822 if (nr > 5) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000823 msg_pdbg2("%s: number of regions too high (%d) - failed\n",
824 __func__, nr);
825 return ICH_RET_ERR;
826 }
827 for (i = 0; i <= nr; i++)
828 desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar);
829
830 /* master section */
831 desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar);
832 desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar);
833 desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar);
834
835 /* Accessing the strap section via FDOC/D is only possible on ICH8 and
836 * reading the upper map is impossible on all chipsets, so don't bother.
837 */
838
839 msg_pdbg2(" done.\n");
840 return ICH_RET_OK;
841}
Stefan Taunerb3850962011-12-24 00:00:32 +0000842#endif /* ICH_DESCRIPTORS_FROM_DUMP */
Stefan Tauner1e146392011-09-15 23:52:55 +0000843#endif /* defined(__i386__) || defined(__x86_64__) */