| Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __SPI_H__ |
| 21 | #define __SPI_H__ 1 |
| 22 | |
| 23 | /* |
| 24 | * Contains the generic SPI headers |
| 25 | */ |
| 26 | |
| 27 | /* Read Electronic ID */ |
| 28 | #define JEDEC_RDID 0x9f |
| 29 | #define JEDEC_RDID_OUTSIZE 0x01 |
| 30 | #define JEDEC_RDID_INSIZE 0x03 |
| 31 | |
| 32 | /* Write Enable */ |
| 33 | #define JEDEC_WREN 0x06 |
| 34 | #define JEDEC_WREN_OUTSIZE 0x01 |
| 35 | #define JEDEC_WREN_INSIZE 0x00 |
| 36 | |
| 37 | /* Write Disable */ |
| 38 | #define JEDEC_WRDI 0x04 |
| 39 | #define JEDEC_WRDI_OUTSIZE 0x01 |
| 40 | #define JEDEC_WRDI_INSIZE 0x00 |
| 41 | |
| 42 | /* Chip Erase 0x60 is supported by Macronix/SST chips. */ |
| 43 | #define JEDEC_CE_60 0x60 |
| 44 | #define JEDEC_CE_60_OUTSIZE 0x01 |
| 45 | #define JEDEC_CE_60_INSIZE 0x00 |
| 46 | |
| 47 | /* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ |
| 48 | #define JEDEC_CE_C7 0xc7 |
| 49 | #define JEDEC_CE_C7_OUTSIZE 0x01 |
| 50 | #define JEDEC_CE_C7_INSIZE 0x00 |
| 51 | |
| 52 | /* Block Erase 0x52 is supported by SST chips. */ |
| 53 | #define JEDEC_BE_52 0x52 |
| 54 | #define JEDEC_BE_52_OUTSIZE 0x04 |
| 55 | #define JEDEC_BE_52_INSIZE 0x00 |
| 56 | |
| 57 | /* Block Erase 0xd8 is supported by EON/Macronix chips. */ |
| 58 | #define JEDEC_BE_D8 0xd8 |
| 59 | #define JEDEC_BE_D8_OUTSIZE 0x04 |
| 60 | #define JEDEC_BE_D8_INSIZE 0x00 |
| 61 | |
| 62 | /* Sector Erase 0x20 is supported by Macronix/SST chips. */ |
| 63 | #define JEDEC_SE 0x20 |
| 64 | #define JEDEC_SE_OUTSIZE 0x04 |
| 65 | #define JEDEC_SE_INSIZE 0x00 |
| 66 | |
| 67 | /* Read Status Register */ |
| 68 | #define JEDEC_RDSR 0x05 |
| 69 | #define JEDEC_RDSR_OUTSIZE 0x01 |
| 70 | #define JEDEC_RDSR_INSIZE 0x01 |
| 71 | #define JEDEC_RDSR_BIT_WIP (0x01 << 0) |
| 72 | |
| 73 | /* Write Status Register */ |
| 74 | #define JEDEC_WRSR 0x01 |
| 75 | #define JEDEC_WRSR_OUTSIZE 0x02 |
| 76 | #define JEDEC_WRSR_INSIZE 0x00 |
| 77 | |
| 78 | /* Read the memory */ |
| 79 | #define JEDEC_READ 0x03 |
| 80 | #define JEDEC_READ_OUTSIZE 0x04 |
| 81 | /* JEDEC_READ_INSIZE : any length */ |
| 82 | |
| 83 | /* Write memory byte */ |
| 84 | #define JEDEC_BYTE_PROGRAM 0x02 |
| 85 | #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 |
| 86 | #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 |
| 87 | |
| 88 | #endif /* !__SPI_H__ */ |