Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Datasheet: |
| 19 | * - Name: Intel 82802AB/82802AC Firmware Hub (FWH) |
| 20 | * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm |
| 21 | * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf |
| 22 | * - Order number: 290658-004 |
| 23 | */ |
| 24 | |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 25 | #include "flash.h" |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 26 | #include "chipdrivers.h" |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 27 | |
Sean Nelson | 28accc2 | 2010-03-19 18:47:06 +0000 | [diff] [blame] | 28 | void print_status_82802ab(uint8_t status) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 29 | { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 30 | msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:"); |
| 31 | msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); |
| 32 | msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); |
| 33 | msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); |
| 34 | msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); |
| 35 | msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); |
| 36 | msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 37 | } |
| 38 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 39 | int probe_82802ab(struct flashctx *flash) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 40 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 41 | chipaddr bios = flash->virtual_memory; |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 42 | uint8_t id1, id2, flashcontent1, flashcontent2; |
Carl-Daniel Hailfinger | a8cf362 | 2014-08-08 08:33:01 +0000 | [diff] [blame] | 43 | int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 44 | |
Carl-Daniel Hailfinger | 4e9cebb | 2009-09-05 01:16:30 +0000 | [diff] [blame] | 45 | /* Reset to get a clean state */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 46 | chip_writeb(flash, 0xFF, bios); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 47 | programmer_delay(10); |
Carl-Daniel Hailfinger | 4e9cebb | 2009-09-05 01:16:30 +0000 | [diff] [blame] | 48 | |
| 49 | /* Enter ID mode */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 50 | chip_writeb(flash, 0x90, bios); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 51 | programmer_delay(10); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 52 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 53 | id1 = chip_readb(flash, bios + (0x00 << shifted)); |
| 54 | id2 = chip_readb(flash, bios + (0x01 << shifted)); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 55 | |
| 56 | /* Leave ID mode */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 57 | chip_writeb(flash, 0xFF, bios); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 58 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 59 | programmer_delay(10); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 60 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 61 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 62 | |
Carl-Daniel Hailfinger | 12aa0be | 2010-03-22 23:47:38 +0000 | [diff] [blame] | 63 | if (!oddparity(id1)) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 64 | msg_cdbg(", id1 parity violation"); |
Carl-Daniel Hailfinger | 12aa0be | 2010-03-22 23:47:38 +0000 | [diff] [blame] | 65 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 66 | /* |
| 67 | * Read the product ID location again. We should now see normal |
| 68 | * flash contents. |
| 69 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 70 | flashcontent1 = chip_readb(flash, bios + (0x00 << shifted)); |
| 71 | flashcontent2 = chip_readb(flash, bios + (0x01 << shifted)); |
Carl-Daniel Hailfinger | 12aa0be | 2010-03-22 23:47:38 +0000 | [diff] [blame] | 72 | |
| 73 | if (id1 == flashcontent1) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 74 | msg_cdbg(", id1 is normal flash content"); |
Carl-Daniel Hailfinger | 12aa0be | 2010-03-22 23:47:38 +0000 | [diff] [blame] | 75 | if (id2 == flashcontent2) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 76 | msg_cdbg(", id2 is normal flash content"); |
Carl-Daniel Hailfinger | 12aa0be | 2010-03-22 23:47:38 +0000 | [diff] [blame] | 77 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 78 | msg_cdbg("\n"); |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 79 | if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 80 | return 0; |
| 81 | |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 82 | return 1; |
| 83 | } |
| 84 | |
Stefan Tauner | 4404f73 | 2013-09-12 08:28:56 +0000 | [diff] [blame] | 85 | /* FIXME: needs timeout */ |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 86 | uint8_t wait_82802ab(struct flashctx *flash) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 87 | { |
| 88 | uint8_t status; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 89 | chipaddr bios = flash->virtual_memory; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 90 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 91 | chip_writeb(flash, 0x70, bios); |
| 92 | if ((chip_readb(flash, bios) & 0x80) == 0) { // it's busy |
| 93 | while ((chip_readb(flash, bios) & 0x80) == 0) ; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 96 | status = chip_readb(flash, bios); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 97 | |
Carl-Daniel Hailfinger | 4e9cebb | 2009-09-05 01:16:30 +0000 | [diff] [blame] | 98 | /* Reset to get a clean state */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 99 | chip_writeb(flash, 0xFF, bios); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 100 | |
| 101 | return status; |
| 102 | } |
| 103 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 104 | int erase_block_82802ab(struct flashctx *flash, unsigned int page, |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 105 | unsigned int pagesize) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 106 | { |
Sean Nelson | 5459637 | 2010-01-09 05:30:14 +0000 | [diff] [blame] | 107 | chipaddr bios = flash->virtual_memory; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 108 | uint8_t status; |
| 109 | |
| 110 | // clear status register |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 111 | chip_writeb(flash, 0x50, bios + page); |
Stefan Reinauer | ab044b2 | 2009-09-16 08:26:59 +0000 | [diff] [blame] | 112 | |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 113 | // now start it |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 114 | chip_writeb(flash, 0x20, bios + page); |
| 115 | chip_writeb(flash, 0xd0, bios + page); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 116 | programmer_delay(10); |
Stefan Reinauer | ab044b2 | 2009-09-16 08:26:59 +0000 | [diff] [blame] | 117 | |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 118 | // now let's see what the register is |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 119 | status = wait_82802ab(flash); |
Sean Nelson | 28accc2 | 2010-03-19 18:47:06 +0000 | [diff] [blame] | 120 | print_status_82802ab(status); |
Stefan Reinauer | ab044b2 | 2009-09-16 08:26:59 +0000 | [diff] [blame] | 121 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 122 | /* FIXME: Check the status register for errors. */ |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 123 | return 0; |
| 124 | } |
| 125 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 126 | /* chunksize is 1 */ |
Mark Marshall | f20b7be | 2014-05-09 21:16:21 +0000 | [diff] [blame] | 127 | int write_82802ab(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len) |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 128 | { |
| 129 | int i; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 130 | chipaddr dst = flash->virtual_memory + start; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 131 | |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 132 | for (i = 0; i < len; i++) { |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 133 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 134 | chip_writeb(flash, 0x40, dst); |
| 135 | chip_writeb(flash, *src++, dst++); |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 136 | wait_82802ab(flash); |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 137 | } |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 138 | |
| 139 | /* FIXME: Ignore errors for now. */ |
| 140 | return 0; |
Carl-Daniel Hailfinger | e7bcb19 | 2008-03-14 00:02:25 +0000 | [diff] [blame] | 141 | } |
| 142 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 143 | int unlock_28f004s5(struct flashctx *flash) |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 144 | { |
| 145 | chipaddr bios = flash->virtual_memory; |
Sean Nelson | 4e54de9 | 2010-03-22 07:03:26 +0000 | [diff] [blame] | 146 | uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0; |
| 147 | int i; |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 148 | |
| 149 | /* Clear status register */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 150 | chip_writeb(flash, 0x50, bios); |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 151 | |
| 152 | /* Read identifier codes */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 153 | chip_writeb(flash, 0x90, bios); |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 154 | |
| 155 | /* Read master lock-bit */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 156 | mcfg = chip_readb(flash, bios + 0x3); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 157 | msg_cdbg("master lock is "); |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 158 | if (mcfg) { |
| 159 | msg_cdbg("locked!\n"); |
| 160 | } else { |
| 161 | msg_cdbg("unlocked!\n"); |
| 162 | can_unlock = 1; |
| 163 | } |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 164 | |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 165 | /* Read block lock-bits */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 166 | for (i = 0; i < flash->chip->total_size * 1024; i+= (64 * 1024)) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 167 | bcfg = chip_readb(flash, bios + i + 2); // read block lock config |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 168 | msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); |
| 169 | if (bcfg) { |
| 170 | need_unlock = 1; |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | /* Reset chip */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 175 | chip_writeb(flash, 0xFF, bios); |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 176 | |
| 177 | /* Unlock: clear block lock-bits, if needed */ |
| 178 | if (can_unlock && need_unlock) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 179 | msg_cdbg("Unlock: "); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 180 | chip_writeb(flash, 0x60, bios); |
| 181 | chip_writeb(flash, 0xD0, bios); |
| 182 | chip_writeb(flash, 0xFF, bios); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 183 | msg_cdbg("Done!\n"); |
Sean Nelson | dee4a83 | 2010-03-22 04:39:31 +0000 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | /* Error: master locked or a block is locked */ |
| 187 | if (!can_unlock && need_unlock) { |
| 188 | msg_cerr("At least one block is locked and lockdown is active!\n"); |
| 189 | return -1; |
| 190 | } |
| 191 | |
| 192 | return 0; |
| 193 | } |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 194 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 195 | int unlock_lh28f008bjt(struct flashctx *flash) |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 196 | { |
| 197 | chipaddr bios = flash->virtual_memory; |
| 198 | uint8_t mcfg, bcfg; |
| 199 | uint8_t need_unlock = 0, can_unlock = 0; |
| 200 | int i; |
| 201 | |
| 202 | /* Wait if chip is busy */ |
| 203 | wait_82802ab(flash); |
| 204 | |
| 205 | /* Read identifier codes */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 206 | chip_writeb(flash, 0x90, bios); |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 207 | |
| 208 | /* Read master lock-bit */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 209 | mcfg = chip_readb(flash, bios + 0x3); |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 210 | msg_cdbg("master lock is "); |
| 211 | if (mcfg) { |
| 212 | msg_cdbg("locked!\n"); |
| 213 | } else { |
| 214 | msg_cdbg("unlocked!\n"); |
| 215 | can_unlock = 1; |
| 216 | } |
| 217 | |
| 218 | /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 219 | for (i = 0; i < flash->chip->total_size * 1024; |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 220 | i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 221 | bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */ |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 222 | msg_cdbg("block lock at %06x is %slocked!\n", i, |
| 223 | bcfg ? "" : "un"); |
| 224 | if (bcfg) |
| 225 | need_unlock = 1; |
| 226 | } |
| 227 | |
| 228 | /* Reset chip */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 229 | chip_writeb(flash, 0xFF, bios); |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 230 | |
| 231 | /* Unlock: clear block lock-bits, if needed */ |
| 232 | if (can_unlock && need_unlock) { |
| 233 | msg_cdbg("Unlock: "); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 234 | chip_writeb(flash, 0x60, bios); |
| 235 | chip_writeb(flash, 0xD0, bios); |
| 236 | chip_writeb(flash, 0xFF, bios); |
Mattias Mattsson | fca3b01 | 2011-08-25 22:44:11 +0000 | [diff] [blame] | 237 | wait_82802ab(flash); |
| 238 | msg_cdbg("Done!\n"); |
| 239 | } |
| 240 | |
| 241 | /* Error: master locked or a block is locked */ |
| 242 | if (!can_unlock && need_unlock) { |
| 243 | msg_cerr("At least one block is locked and lockdown is active!\n"); |
| 244 | return -1; |
| 245 | } |
| 246 | |
| 247 | return 0; |
| 248 | } |