blob: a4878d2c2a024240d70be413c1daa24b1750a4f5 [file] [log] [blame]
Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
Uwe Hermann92c53ee2009-05-13 12:01:57 +000023#include <sys/types.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000024#include "flash.h"
25
26#define BIOS_ROM_ADDR 0x04
27#define BIOS_ROM_DATA 0x08
28#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000029#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000030#define SELECT_REG_WINDOW 0x800
31
Uwe Hermannb4dcb712009-05-13 11:36:06 +000032#define PCI_VENDOR_ID_3COM 0x10b7
33
Uwe Hermann8403ccb2009-05-16 21:39:19 +000034uint32_t internal_conf;
35uint16_t id;
36
Uwe Hermann515ab3d2009-05-15 17:02:34 +000037struct pcidev_status nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000038 /* 3C90xB */
Uwe Hermann8403ccb2009-05-16 21:39:19 +000039 {0x10b7, 0x9055, PCI_OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
Uwe Hermann515ab3d2009-05-15 17:02:34 +000040 {0x10b7, 0x9001, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
Carl-Daniel Hailfingerfdb852f2009-08-24 01:47:33 +000041 {0x10b7, 0x9004, PCI_OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
Uwe Hermann515ab3d2009-05-15 17:02:34 +000042 {0x10b7, 0x9005, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
43 {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
44 {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" },
45 {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" },
Uwe Hermanne9d04d42009-06-02 19:54:22 +000046 {0x10b7, 0x9058, PCI_OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000047
48 /* 3C905C */
Uwe Hermann515ab3d2009-05-15 17:02:34 +000049 {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000050
51 /* 3C980C */
Uwe Hermann515ab3d2009-05-15 17:02:34 +000052 {0x10b7, 0x9805, PCI_NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000053
54 {},
55};
56
57int nic3com_init(void)
58{
Uwe Hermanna0869322009-05-14 20:41:57 +000059 get_io_perms();
Uwe Hermannb4dcb712009-05-13 11:36:06 +000060
TURBO Jb0912c02009-09-02 23:00:46 +000061 io_base_addr = pcidev_init(PCI_VENDOR_ID_3COM, PCI_BASE_ADDRESS_0,
62 nics_3com, programmer_param);
Uwe Hermann8403ccb2009-05-16 21:39:19 +000063 id = pcidev_dev->device_id;
64
65 /* 3COM 3C90xB cards need a special fixup. */
66 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000067 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000068 /* Select register window 3 and save the receiver status. */
69 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
70 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
71
72 /* Set receiver type to MII for full BIOS ROM access. */
73 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
74 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +000075
76 /*
77 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
78 * cards form a 'register window' into one of multiple (usually 8)
79 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
80 */
81 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
82
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000083 buses_supported = CHIP_BUSTYPE_PARALLEL;
84
Uwe Hermannb4dcb712009-05-13 11:36:06 +000085 return 0;
86}
87
88int nic3com_shutdown(void)
89{
Uwe Hermann8403ccb2009-05-16 21:39:19 +000090 /* 3COM 3C90xB cards need a special fixup. */
91 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000092 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000093 /* Select register window 3 and restore the receiver status. */
94 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
95 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
96 }
97
Carl-Daniel Hailfingeref58a9c2009-08-12 13:32:56 +000098 free(programmer_param);
Christian Ruppert0cdb0312009-05-14 18:57:26 +000099 pci_cleanup(pacc);
Carl-Daniel Hailfingerdb41c592009-08-09 21:50:24 +0000100 release_io_perms();
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000101 return 0;
102}
103
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000104void nic3com_chip_writeb(uint8_t val, chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000105{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000106 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000107 OUTB(val, io_base_addr + BIOS_ROM_DATA);
108}
109
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000110uint8_t nic3com_chip_readb(const chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000111{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000112 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannc7e8a0c2009-05-19 14:14:21 +0000113 return INB(io_base_addr + BIOS_ROM_DATA);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000114}