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Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Joerg Fischer52a15492010-05-21 22:28:19 +000015 */
16
17#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000018#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000019#include "programmer.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010020#include "hwaccess_x86_io.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010021#include "platform/pci.h"
Joerg Fischer52a15492010-05-21 22:28:19 +000022
23#define PCI_VENDOR_ID_REALTEK 0x10ec
24#define PCI_VENDOR_ID_SMC1211 0x1113
25
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000026static uint32_t io_base_addr = 0;
Sergey Lichack98f47102012-08-27 01:24:15 +000027static int bios_rom_addr, bios_rom_data;
Joerg Fischer52a15492010-05-21 22:28:19 +000028
Thomas Heijligencc853d82021-05-04 15:32:17 +020029static const struct dev_entry nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000030 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Sergey Lichack98f47102012-08-27 01:24:15 +000031 {0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
32 {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000033
34 {0},
Joerg Fischer52a15492010-05-21 22:28:19 +000035};
36
Sergey Lichack98f47102012-08-27 01:24:15 +000037static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
38static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
Anastasia Klimchukd66dded2021-08-27 15:42:46 +100039static int nicrealtek_shutdown(void *data);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000040static const struct par_master par_master_nicrealtek = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020041 .chip_readb = nicrealtek_chip_readb,
42 .chip_readw = fallback_chip_readw,
43 .chip_readl = fallback_chip_readl,
44 .chip_readn = fallback_chip_readn,
45 .chip_writeb = nicrealtek_chip_writeb,
46 .chip_writew = fallback_chip_writew,
47 .chip_writel = fallback_chip_writel,
48 .chip_writen = fallback_chip_writen,
Anastasia Klimchukd66dded2021-08-27 15:42:46 +100049 .shutdown = nicrealtek_shutdown,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000050};
51
David Hendricks8bb20212011-06-14 01:35:36 +000052static int nicrealtek_shutdown(void *data)
53{
54 /* FIXME: We forgot to disable software access again. */
David Hendricks8bb20212011-06-14 01:35:36 +000055 return 0;
56}
57
Thomas Heijligencc853d82021-05-04 15:32:17 +020058static int nicrealtek_init(void)
Joerg Fischer52a15492010-05-21 22:28:19 +000059{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000060 struct pci_dev *dev = NULL;
61
Stefan Taunerd7d423b2012-10-20 09:13:16 +000062 if (rget_io_perms())
63 return 1;
64
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000065 dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0);
66 if (!dev)
Stefan Taunerd7d423b2012-10-20 09:13:16 +000067 return 1;
68
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000069 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000070 if (!io_base_addr)
71 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000072
Sergey Lichack98f47102012-08-27 01:24:15 +000073 /* Beware, this ignores the vendor ID! */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000074 switch (dev->device_id) {
Sergey Lichack98f47102012-08-27 01:24:15 +000075 case 0x8139: /* RTL8139 */
76 case 0x1211: /* SMC 1211TX */
77 default:
78 bios_rom_addr = 0xD4;
79 bios_rom_data = 0xD7;
80 break;
81 case 0x8169: /* RTL8169 */
82 bios_rom_addr = 0x30;
83 bios_rom_data = 0x33;
84 break;
85 }
86
Anastasia Klimchukd66dded2021-08-27 15:42:46 +100087 return register_par_master(&par_master_nicrealtek, BUS_PARALLEL, NULL);
Joerg Fischer52a15492010-05-21 22:28:19 +000088}
89
Sergey Lichack98f47102012-08-27 01:24:15 +000090static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000091{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000092 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
93 * enable software access.
94 */
Uwe Hermann829ed842010-05-24 17:39:14 +000095 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +000096 io_base_addr + bios_rom_addr);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000097 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
98 * enable software access.
99 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000100 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000101 io_base_addr + bios_rom_addr);
Joerg Fischer52a15492010-05-21 22:28:19 +0000102}
103
Sergey Lichack98f47102012-08-27 01:24:15 +0000104static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +0000105{
Uwe Hermann829ed842010-05-24 17:39:14 +0000106 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000107
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000108 /* FIXME: Can we skip reading the old data and simply use 0? */
109 /* Read old data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000110 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000111 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
112 * enable software access.
113 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000114 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000115 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000116
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000117 /* Read new data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000118 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000119 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
120 * enable software access.
121 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000122 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000123 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000124
125 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000126}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000127
Thomas Heijligencc853d82021-05-04 15:32:17 +0200128const struct programmer_entry programmer_nicrealtek = {
129 .name = "nicrealtek",
130 .type = PCI,
131 .devs.dev = nics_realtek,
132 .init = nicrealtek_init,
133 .map_flash_region = fallback_map,
134 .unmap_flash_region = fallback_unmap,
135 .delay = internal_delay,
136};