blob: 125077c64b6d470fd49a9be0b4c9de8e761b6845 [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#if defined(__i386__) || defined(__x86_64__)
23
24#include "ich_descriptors.h"
25#include "flash.h" /* for msg_* */
26#include "programmer.h"
27
28void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity)
29{
30 print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
31 print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
32 print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
33 print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
34 print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
35 print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
36}
37
38#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0)
39#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0)
40#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0)
41#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0)
42#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0)
43
44void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc)
45{
46 prettyprint_ich_descriptor_content(&desc->content);
47 prettyprint_ich_descriptor_component(desc);
48 prettyprint_ich_descriptor_region(desc);
49 prettyprint_ich_descriptor_master(&desc->master);
50}
51
52void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont)
53{
54 msg_pdbg2("=== Content Section ===\n");
55 msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG);
56 msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0);
57 msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1);
58 msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2);
59 msg_pdbg2("\n");
60
61 msg_pdbg2("--- Details ---\n");
62 msg_pdbg2("NR (Number of Regions): %5d\n",
63 cont->NR + 1);
64 msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n",
65 getFRBA(cont));
66 msg_pdbg2("NC (Number of Components): %5d\n",
67 cont->NC + 1);
68 msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n",
69 getFCBA(cont));
70 msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n",
71 cont->ISL);
72 msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n",
73 getFISBA(cont));
74 msg_pdbg2("NM (Number of Masters): %5d\n",
75 cont->NM + 1);
76 msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n",
77 getFMBA(cont));
78 msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n",
79 cont->MSL);
80 msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n",
81 getFMSBA(cont));
82 msg_pdbg2("\n");
83}
84
85void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc)
86{
87 static const char * const freq_str[8] = {
88 "20 MHz", /* 000 */
89 "33 MHz", /* 001 */
90 "reserved", /* 010 */
91 "reserved", /* 011 */
92 "50 MHz", /* 100 */
93 "reserved", /* 101 */
94 "reserved", /* 110 */
95 "reserved" /* 111 */
96 };
97 static const char * const size_str[8] = {
98 "512 kB", /* 000 */
99 " 1 MB", /* 001 */
100 " 2 MB", /* 010 */
101 " 4 MB", /* 011 */
102 " 8 MB", /* 100 */
103 " 16 MB", /* 101 */
104 "reserved", /* 110 */
105 "reserved", /* 111 */
106 };
107
108 msg_pdbg2("=== Component Section ===\n");
109 msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP);
110 msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL );
111 msg_pdbg2("\n");
112
113 msg_pdbg2("--- Details ---\n");
114 msg_pdbg2("Component 1 density: %s\n",
115 size_str[desc->component.comp1_density]);
116 if (desc->content.NC)
117 msg_pdbg2("Component 2 density: %s\n",
118 size_str[desc->component.comp2_density]);
119 else
120 msg_pdbg2("Component 2 is not used.\n");
121 msg_pdbg2("Read Clock Frequency: %s\n",
122 freq_str[desc->component.freq_read]);
123 msg_pdbg2("Read ID and Status Clock Freq.: %s\n",
124 freq_str[desc->component.freq_read_id]);
125 msg_pdbg2("Write and Erase Clock Freq.: %s\n",
126 freq_str[desc->component.freq_write]);
127 msg_pdbg2("Fast Read is %ssupported.\n",
128 desc->component.fastread ? "" : "not ");
129 if (desc->component.fastread)
130 msg_pdbg2("Fast Read Clock Frequency: %s\n",
131 freq_str[desc->component.freq_fastread]);
132 if (desc->component.FLILL == 0)
133 msg_pdbg2("No forbidden opcodes.\n");
134 else {
135 msg_pdbg2("Invalid instruction 0: 0x%02x\n",
136 desc->component.invalid_instr0);
137 msg_pdbg2("Invalid instruction 1: 0x%02x\n",
138 desc->component.invalid_instr1);
139 msg_pdbg2("Invalid instruction 2: 0x%02x\n",
140 desc->component.invalid_instr2);
141 msg_pdbg2("Invalid instruction 3: 0x%02x\n",
142 desc->component.invalid_instr3);
143 }
144 msg_pdbg2("\n");
145}
146
147static void pprint_freg(const struct ich_desc_region *reg, uint32_t i)
148{
149 static const char *const region_names[5] = {
150 "Descr.", "BIOS", "ME", "GbE", "Platf."
151 };
152 if (i >= 5) {
153 msg_pdbg2("%s: region index too high.\n", __func__);
154 return;
155 }
156 uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]);
157 uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]);
158 msg_pdbg2("Region %d (%-6s) ", i, region_names[i]);
159 if (base > limit)
160 msg_pdbg2("is unused.\n");
161 else
162 msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff);
163}
164
165void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc)
166{
167 uint8_t i;
168 uint8_t nr = desc->content.NR + 1;
169 msg_pdbg2("=== Region Section ===\n");
170 if (nr >= 5) {
171 msg_pdbg2("%s: number of regions too high (%d).\n", __func__,
172 nr);
173 return;
174 }
175 for (i = 0; i <= nr; i++)
176 msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]);
177 msg_pdbg2("\n");
178
179 msg_pdbg2("--- Details ---\n");
180 for (i = 0; i <= nr; i++)
181 pprint_freg(&desc->region, i);
182 msg_pdbg2("\n");
183}
184
185void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr)
186{
187 msg_pdbg2("=== Master Section ===\n");
188 msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1);
189 msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2);
190 msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3);
191 msg_pdbg2("\n");
192
193 msg_pdbg2("--- Details ---\n");
194 msg_pdbg2(" Descr. BIOS ME GbE Platf.\n");
195 msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n",
196 (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ',
197 (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ',
198 (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ',
199 (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ',
200 (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' ');
201 msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n",
202 (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ',
203 (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ',
204 (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ',
205 (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ',
206 (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' ');
207 msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n",
208 (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ',
209 (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ',
210 (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ',
211 (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ',
212 (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' ');
213 msg_pdbg2("\n");
214}
215
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000216/** Returns the integer representation of the component density with index
217idx in bytes or 0 if a correct size can not be determined. */
218int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx)
219{
220 uint8_t size_enc;
221
222 switch(idx) {
223 case 0:
224 size_enc = desc->component.comp1_density;
225 break;
226 case 1:
227 if (desc->content.NC == 0)
228 return 0;
229 size_enc = desc->component.comp2_density;
230 break;
231 default:
232 msg_perr("Only ICH SPI component index 0 or 1 are supported "
233 "yet.\n");
234 return 0;
235 }
236 if (size_enc > 5) {
237 msg_perr("Density of ICH SPI component with index %d is "
238 "invalid. Encoded density is 0x%x.\n", idx, size_enc);
239 return 0;
240 }
241 return (1 << (19 + size_enc));
242}
243
Stefan Tauner1e146392011-09-15 23:52:55 +0000244static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar)
245{
246 uint32_t control = 0;
247 control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS;
248 control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI;
249 mmio_le_writel(control, spibar + ICH9_REG_FDOC);
250 return mmio_le_readl(spibar + ICH9_REG_FDOD);
251}
252
253int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
254{
255 uint8_t i;
256 uint8_t nr;
257 struct ich_desc_region *r = &desc->region;
258
259 /* Test if bit-fields are working as expected.
260 * FIXME: Replace this with dynamic bitfield fixup
261 */
262 for (i = 0; i < 4; i++)
263 desc->region.FLREGs[i] = 0x5A << (i * 8);
264 if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 ||
265 r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 ||
266 r->reg2_base != 0x0000 || r->reg2_limit != 0x005A ||
267 r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) {
268 msg_pdbg("The combination of compiler and CPU architecture used"
269 "does not lay out bit-fields as expected, sorry.\n");
270 msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base);
271 msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit);
272 msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base);
273 msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit);
274 msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base);
275 msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit);
276 msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base);
277 msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit);
278 return ICH_RET_ERR;
279 }
280
281 msg_pdbg2("Reading flash descriptors "
282 "mapped by the chipset via FDOC/FDOD...");
283 /* content section */
284 desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar);
285 desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar);
286 desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar);
287 desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar);
288
289 /* component section */
290 desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar);
291 desc->component.FLILL = read_descriptor_reg(1, 1, spibar);
292 desc->component.FLPB = read_descriptor_reg(1, 2, spibar);
293
294 /* region section */
295 nr = desc->content.NR + 1;
296 if (nr >= 5) {
297 msg_pdbg2("%s: number of regions too high (%d) - failed\n",
298 __func__, nr);
299 return ICH_RET_ERR;
300 }
301 for (i = 0; i <= nr; i++)
302 desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar);
303
304 /* master section */
305 desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar);
306 desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar);
307 desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar);
308
309 /* Accessing the strap section via FDOC/D is only possible on ICH8 and
310 * reading the upper map is impossible on all chipsets, so don't bother.
311 */
312
313 msg_pdbg2(" done.\n");
314 return ICH_RET_OK;
315}
316#endif /* defined(__i386__) || defined(__x86_64__) */