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Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Joerg Fischer52a15492010-05-21 22:28:19 +000023#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000024#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000026#include "hwaccess.h"
Joerg Fischer52a15492010-05-21 22:28:19 +000027
28#define PCI_VENDOR_ID_REALTEK 0x10ec
29#define PCI_VENDOR_ID_SMC1211 0x1113
30
Sergey Lichack98f47102012-08-27 01:24:15 +000031static int bios_rom_addr, bios_rom_data;
Joerg Fischer52a15492010-05-21 22:28:19 +000032
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000033const struct dev_entry nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000034 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Sergey Lichack98f47102012-08-27 01:24:15 +000035 {0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
36 {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000037
38 {0},
Joerg Fischer52a15492010-05-21 22:28:19 +000039};
40
Sergey Lichack98f47102012-08-27 01:24:15 +000041static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
42static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000043static const struct par_programmer par_programmer_nicrealtek = {
44 .chip_readb = nicrealtek_chip_readb,
45 .chip_readw = fallback_chip_readw,
46 .chip_readl = fallback_chip_readl,
47 .chip_readn = fallback_chip_readn,
48 .chip_writeb = nicrealtek_chip_writeb,
49 .chip_writew = fallback_chip_writew,
50 .chip_writel = fallback_chip_writel,
51 .chip_writen = fallback_chip_writen,
52};
53
David Hendricks8bb20212011-06-14 01:35:36 +000054static int nicrealtek_shutdown(void *data)
55{
56 /* FIXME: We forgot to disable software access again. */
57 pci_cleanup(pacc);
David Hendricks8bb20212011-06-14 01:35:36 +000058 return 0;
59}
60
Joerg Fischer52a15492010-05-21 22:28:19 +000061int nicrealtek_init(void)
62{
Stefan Taunerd7d423b2012-10-20 09:13:16 +000063 if (rget_io_perms())
64 return 1;
65
66 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
67
68 if (register_shutdown(nicrealtek_shutdown, NULL))
69 return 1;
70
Sergey Lichack98f47102012-08-27 01:24:15 +000071 /* Beware, this ignores the vendor ID! */
72 switch (pcidev_dev->device_id) {
73 case 0x8139: /* RTL8139 */
74 case 0x1211: /* SMC 1211TX */
75 default:
76 bios_rom_addr = 0xD4;
77 bios_rom_data = 0xD7;
78 break;
79 case 0x8169: /* RTL8169 */
80 bios_rom_addr = 0x30;
81 bios_rom_data = 0x33;
82 break;
83 }
84
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000085 register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
86
Joerg Fischer52a15492010-05-21 22:28:19 +000087 return 0;
88}
89
Sergey Lichack98f47102012-08-27 01:24:15 +000090static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000091{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000092 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
93 * enable software access.
94 */
Uwe Hermann829ed842010-05-24 17:39:14 +000095 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +000096 io_base_addr + bios_rom_addr);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000097 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
98 * enable software access.
99 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000100 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000101 io_base_addr + bios_rom_addr);
Joerg Fischer52a15492010-05-21 22:28:19 +0000102}
103
Sergey Lichack98f47102012-08-27 01:24:15 +0000104static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +0000105{
Uwe Hermann829ed842010-05-24 17:39:14 +0000106 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000107
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000108 /* FIXME: Can we skip reading the old data and simply use 0? */
109 /* Read old data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000110 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000111 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
112 * enable software access.
113 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000114 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000115 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000116
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000117 /* Read new data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000118 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000119 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
120 * enable software access.
121 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000122 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000123 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000124
125 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000126}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000127
128#else
129#error PCI port I/O access is not supported on this architecture yet.
130#endif