Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 10 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 15 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 21 | #include <stdio.h> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 22 | #include <stdint.h> |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 23 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 24 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 25 | int probe_29f002(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 26 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame^] | 27 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 28 | uint8_t id1, id2; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 29 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 30 | chip_writeb(0xAA, bios + 0x5555); |
| 31 | chip_writeb(0x55, bios + 0x2AAA); |
| 32 | chip_writeb(0x90, bios + 0x5555); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 33 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 34 | id1 = chip_readb(bios); |
| 35 | id2 = chip_readb(bios + 0x01); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 36 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 37 | chip_writeb(0xF0, bios); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 38 | |
Ronald G. Minnich | ef5779d | 2002-01-29 20:18:02 +0000 | [diff] [blame] | 39 | myusec_delay(10); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 40 | |
Peter Stuge | 5cafc33 | 2009-01-25 23:52:45 +0000 | [diff] [blame] | 41 | printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 42 | if (id1 == flash->manufacture_id && id2 == flash->model_id) |
| 43 | return 1; |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 48 | int erase_29f002(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 49 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame^] | 50 | chipaddr bios = flash->virtual_memory; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 51 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 52 | chip_writeb(0xF0, bios + 0x555); |
| 53 | chip_writeb(0xAA, bios + 0x555); |
| 54 | chip_writeb(0x55, bios + 0x2AA); |
| 55 | chip_writeb(0x80, bios + 0x555); |
| 56 | chip_writeb(0xAA, bios + 0x555); |
| 57 | chip_writeb(0x55, bios + 0x2AA); |
| 58 | chip_writeb(0x10, bios + 0x555); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 59 | |
Ronald G. Minnich | ef5779d | 2002-01-29 20:18:02 +0000 | [diff] [blame] | 60 | myusec_delay(100); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 61 | toggle_ready_jedec(bios); |
| 62 | |
| 63 | // while ((*bios & 0x40) != 0x40) |
| 64 | //; |
| 65 | |
| 66 | #if 0 |
| 67 | toggle_ready_jedec(bios); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 68 | chip_writeb(0x30, bios + 0x0ffff); |
| 69 | chip_writeb(0x30, bios + 0x1ffff); |
| 70 | chip_writeb(0x30, bios + 0x2ffff); |
| 71 | chip_writeb(0x30, bios + 0x37fff); |
| 72 | chip_writeb(0x30, bios + 0x39fff); |
| 73 | chip_writeb(0x30, bios + 0x3bfff); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 74 | #endif |
| 75 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 76 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 79 | int write_29f002(struct flashchip *flash, uint8_t *buf) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 80 | { |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 81 | int i; |
| 82 | int total_size = flash->total_size * 1024; |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame^] | 83 | chipaddr bios = flash->virtual_memory; |
| 84 | chipaddr dst = bios; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 85 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 86 | chip_writeb(0xF0, bios); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 87 | myusec_delay(10); |
| 88 | erase_29f002(flash); |
| 89 | //*bios = 0xF0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 90 | #if 1 |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 91 | printf("Programming page: "); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 92 | for (i = 0; i < total_size; i++) { |
| 93 | /* write to the sector */ |
| 94 | if ((i & 0xfff) == 0) |
Uwe Hermann | 0b7afe6 | 2007-04-01 19:44:21 +0000 | [diff] [blame] | 95 | printf("address: 0x%08lx", (unsigned long)i); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 96 | chip_writeb(0xAA, bios + 0x5555); |
| 97 | chip_writeb(0x55, bios + 0x2AAA); |
| 98 | chip_writeb(0xA0, bios + 0x5555); |
| 99 | chip_writeb(*buf++, dst++); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 100 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 101 | /* wait for Toggle bit ready */ |
| 102 | toggle_ready_jedec(dst); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 103 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 104 | if ((i & 0xfff) == 0) |
| 105 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
| 106 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 107 | #endif |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 108 | printf("\n"); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 109 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 110 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 111 | } |