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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 */
20
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000021#include <stdio.h>
Ollie Lho184a4042005-11-26 21:55:36 +000022#include <stdint.h>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000024
Ollie Lho761bf1b2004-03-20 16:46:10 +000025int probe_29f002(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000026{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000027 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000028 uint8_t id1, id2;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000029
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000030 chip_writeb(0xAA, bios + 0x5555);
31 chip_writeb(0x55, bios + 0x2AAA);
32 chip_writeb(0x90, bios + 0x5555);
Ollie Lho761bf1b2004-03-20 16:46:10 +000033
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000034 id1 = chip_readb(bios);
35 id2 = chip_readb(bios + 0x01);
Ollie Lho761bf1b2004-03-20 16:46:10 +000036
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000037 chip_writeb(0xF0, bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000038
Ronald G. Minnichef5779d2002-01-29 20:18:02 +000039 myusec_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000040
Peter Stuge5cafc332009-01-25 23:52:45 +000041 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000042 if (id1 == flash->manufacture_id && id2 == flash->model_id)
43 return 1;
44
45 return 0;
46}
47
Ollie Lho761bf1b2004-03-20 16:46:10 +000048int erase_29f002(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000049{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000050 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000051
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000052 chip_writeb(0xF0, bios + 0x555);
53 chip_writeb(0xAA, bios + 0x555);
54 chip_writeb(0x55, bios + 0x2AA);
55 chip_writeb(0x80, bios + 0x555);
56 chip_writeb(0xAA, bios + 0x555);
57 chip_writeb(0x55, bios + 0x2AA);
58 chip_writeb(0x10, bios + 0x555);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000059
Ronald G. Minnichef5779d2002-01-29 20:18:02 +000060 myusec_delay(100);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000061 toggle_ready_jedec(bios);
62
63 // while ((*bios & 0x40) != 0x40)
64 //;
65
66#if 0
67 toggle_ready_jedec(bios);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000068 chip_writeb(0x30, bios + 0x0ffff);
69 chip_writeb(0x30, bios + 0x1ffff);
70 chip_writeb(0x30, bios + 0x2ffff);
71 chip_writeb(0x30, bios + 0x37fff);
72 chip_writeb(0x30, bios + 0x39fff);
73 chip_writeb(0x30, bios + 0x3bfff);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000074#endif
75
Uwe Hermannffec5f32007-08-23 16:08:21 +000076 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000077}
78
Ollie Lho184a4042005-11-26 21:55:36 +000079int write_29f002(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000080{
Ollie Lho761bf1b2004-03-20 16:46:10 +000081 int i;
82 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000083 chipaddr bios = flash->virtual_memory;
84 chipaddr dst = bios;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000085
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000086 chip_writeb(0xF0, bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +000087 myusec_delay(10);
88 erase_29f002(flash);
89 //*bios = 0xF0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000090#if 1
Uwe Hermanna502dce2007-10-17 23:55:15 +000091 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +000092 for (i = 0; i < total_size; i++) {
93 /* write to the sector */
94 if ((i & 0xfff) == 0)
Uwe Hermann0b7afe62007-04-01 19:44:21 +000095 printf("address: 0x%08lx", (unsigned long)i);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000096 chip_writeb(0xAA, bios + 0x5555);
97 chip_writeb(0x55, bios + 0x2AAA);
98 chip_writeb(0xA0, bios + 0x5555);
99 chip_writeb(*buf++, dst++);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000100
Ollie Lho761bf1b2004-03-20 16:46:10 +0000101 /* wait for Toggle bit ready */
102 toggle_ready_jedec(dst);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000103
Ollie Lho761bf1b2004-03-20 16:46:10 +0000104 if ((i & 0xfff) == 0)
105 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
106 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000107#endif
Ollie Lho761bf1b2004-03-20 16:46:10 +0000108 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000109
Uwe Hermannffec5f32007-08-23 16:08:21 +0000110 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000111}