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Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Datasheet:
23 * - Name: Intel 82802AB/82802AC Firmware Hub (FWH)
24 * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm
25 * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf
26 * - Order number: 290658-004
27 */
28
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000029#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "chipdrivers.h"
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000031
Sean Nelson28accc22010-03-19 18:47:06 +000032void print_status_82802ab(uint8_t status)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000033{
Sean Nelsoned479d22010-03-24 23:14:32 +000034 msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
35 msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
36 msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
37 msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
38 msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
39 msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
40 msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000041}
42
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000043int probe_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000044{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000045 chipaddr bios = flash->virtual_memory;
Uwe Hermann91f4afa2011-07-28 08:13:25 +000046 uint8_t id1, id2, flashcontent1, flashcontent2;
Carl-Daniel Hailfingera8cf3622014-08-08 08:33:01 +000047 int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000048
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000049 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000050 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000051 programmer_delay(10);
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000052
53 /* Enter ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000054 chip_writeb(flash, 0x90, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000055 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000056
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000057 id1 = chip_readb(flash, bios + (0x00 << shifted));
58 id2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000059
60 /* Leave ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000061 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000062
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000063 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000064
Sean Nelsoned479d22010-03-24 23:14:32 +000065 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000066
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000067 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +000068 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000069
Uwe Hermann91f4afa2011-07-28 08:13:25 +000070 /*
71 * Read the product ID location again. We should now see normal
72 * flash contents.
73 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000074 flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
75 flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000076
77 if (id1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +000078 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000079 if (id2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +000080 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000081
Sean Nelsoned479d22010-03-24 23:14:32 +000082 msg_cdbg("\n");
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000083 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000084 return 0;
85
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000086 return 1;
87}
88
Stefan Tauner4404f732013-09-12 08:28:56 +000089/* FIXME: needs timeout */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000090uint8_t wait_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000091{
92 uint8_t status;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000093 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000094
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000095 chip_writeb(flash, 0x70, bios);
96 if ((chip_readb(flash, bios) & 0x80) == 0) { // it's busy
97 while ((chip_readb(flash, bios) & 0x80) == 0) ;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000098 }
99
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000100 status = chip_readb(flash, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000101
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +0000102 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000103 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000104
105 return status;
106}
107
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000108int erase_block_82802ab(struct flashctx *flash, unsigned int page,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000109 unsigned int pagesize)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000110{
Sean Nelson54596372010-01-09 05:30:14 +0000111 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000112 uint8_t status;
113
114 // clear status register
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000115 chip_writeb(flash, 0x50, bios + page);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000116
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000117 // now start it
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000118 chip_writeb(flash, 0x20, bios + page);
119 chip_writeb(flash, 0xd0, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000120 programmer_delay(10);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000121
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000122 // now let's see what the register is
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000123 status = wait_82802ab(flash);
Sean Nelson28accc22010-03-19 18:47:06 +0000124 print_status_82802ab(status);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000125
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000126 /* FIXME: Check the status register for errors. */
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000127 return 0;
128}
129
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000130/* chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000131int write_82802ab(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000132{
133 int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000134 chipaddr dst = flash->virtual_memory + start;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000135
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000136 for (i = 0; i < len; i++) {
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000137 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000138 chip_writeb(flash, 0x40, dst);
139 chip_writeb(flash, *src++, dst++);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000140 wait_82802ab(flash);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000141 }
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000142
143 /* FIXME: Ignore errors for now. */
144 return 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000145}
146
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000147int unlock_28f004s5(struct flashctx *flash)
Sean Nelsondee4a832010-03-22 04:39:31 +0000148{
149 chipaddr bios = flash->virtual_memory;
Sean Nelson4e54de92010-03-22 07:03:26 +0000150 uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0;
151 int i;
Sean Nelsondee4a832010-03-22 04:39:31 +0000152
153 /* Clear status register */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000154 chip_writeb(flash, 0x50, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000155
156 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000157 chip_writeb(flash, 0x90, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000158
159 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000160 mcfg = chip_readb(flash, bios + 0x3);
Sean Nelsoned479d22010-03-24 23:14:32 +0000161 msg_cdbg("master lock is ");
Sean Nelsondee4a832010-03-22 04:39:31 +0000162 if (mcfg) {
163 msg_cdbg("locked!\n");
164 } else {
165 msg_cdbg("unlocked!\n");
166 can_unlock = 1;
167 }
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000168
Sean Nelsondee4a832010-03-22 04:39:31 +0000169 /* Read block lock-bits */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000170 for (i = 0; i < flash->chip->total_size * 1024; i+= (64 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000171 bcfg = chip_readb(flash, bios + i + 2); // read block lock config
Sean Nelsondee4a832010-03-22 04:39:31 +0000172 msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un");
173 if (bcfg) {
174 need_unlock = 1;
175 }
176 }
177
178 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000179 chip_writeb(flash, 0xFF, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000180
181 /* Unlock: clear block lock-bits, if needed */
182 if (can_unlock && need_unlock) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000183 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000184 chip_writeb(flash, 0x60, bios);
185 chip_writeb(flash, 0xD0, bios);
186 chip_writeb(flash, 0xFF, bios);
Sean Nelsoned479d22010-03-24 23:14:32 +0000187 msg_cdbg("Done!\n");
Sean Nelsondee4a832010-03-22 04:39:31 +0000188 }
189
190 /* Error: master locked or a block is locked */
191 if (!can_unlock && need_unlock) {
192 msg_cerr("At least one block is locked and lockdown is active!\n");
193 return -1;
194 }
195
196 return 0;
197}
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000198
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000199int unlock_lh28f008bjt(struct flashctx *flash)
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000200{
201 chipaddr bios = flash->virtual_memory;
202 uint8_t mcfg, bcfg;
203 uint8_t need_unlock = 0, can_unlock = 0;
204 int i;
205
206 /* Wait if chip is busy */
207 wait_82802ab(flash);
208
209 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000210 chip_writeb(flash, 0x90, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000211
212 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000213 mcfg = chip_readb(flash, bios + 0x3);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000214 msg_cdbg("master lock is ");
215 if (mcfg) {
216 msg_cdbg("locked!\n");
217 } else {
218 msg_cdbg("unlocked!\n");
219 can_unlock = 1;
220 }
221
222 /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000223 for (i = 0; i < flash->chip->total_size * 1024;
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000224 i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000225 bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000226 msg_cdbg("block lock at %06x is %slocked!\n", i,
227 bcfg ? "" : "un");
228 if (bcfg)
229 need_unlock = 1;
230 }
231
232 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000233 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000234
235 /* Unlock: clear block lock-bits, if needed */
236 if (can_unlock && need_unlock) {
237 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000238 chip_writeb(flash, 0x60, bios);
239 chip_writeb(flash, 0xD0, bios);
240 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000241 wait_82802ab(flash);
242 msg_cdbg("Done!\n");
243 }
244
245 /* Error: master locked or a block is locked */
246 if (!can_unlock && need_unlock) {
247 msg_cerr("At least one block is locked and lockdown is active!\n");
248 return -1;
249 }
250
251 return 0;
252}