blob: c3b93d9771443d11df84b389c5333afb3db43aac [file] [log] [blame]
Andrew Morganc29c2e72010-06-07 22:37:54 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#if defined(__i386__) || defined(__x86_64__)
22
23#include <stdlib.h>
24#include "flash.h"
25
26#define PCI_VENDOR_ID_NATSEMI 0x100b
27
28#define BOOT_ROM_ADDR 0x50
29#define BOOT_ROM_DATA 0x54
30
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000031const struct pcidev_status nics_natsemi[] = {
Andrew Morganc29c2e72010-06-07 22:37:54 +000032 {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
33 {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
34 {},
35};
36
37int nicnatsemi_init(void)
38{
39 get_io_perms();
40
41 io_base_addr = pcidev_init(PCI_VENDOR_ID_NATSEMI, PCI_BASE_ADDRESS_0,
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000042 nics_natsemi);
Andrew Morganc29c2e72010-06-07 22:37:54 +000043
44 buses_supported = CHIP_BUSTYPE_PARALLEL;
45
46 return 0;
47}
48
49int nicnatsemi_shutdown(void)
50{
Andrew Morganc29c2e72010-06-07 22:37:54 +000051 pci_cleanup(pacc);
52 release_io_perms();
53 return 0;
54}
55
56void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr)
57{
58 OUTL((uint32_t)addr & 0x0000FFFF, io_base_addr + BOOT_ROM_ADDR);
59 /*
60 * The datasheet requires 32 bit accesses to this register, but it seems
61 * that requirement might only apply if the register is memory mapped.
62 * Bit 8-31 of this register are apparently don't care, and if this
63 * register is I/O port mapped 8 bit accesses to the lowest byte of the
64 * register seem to work fine. Due to that, we ignore the advice in the
65 * data sheet.
66 */
67 OUTB(val, io_base_addr + BOOT_ROM_DATA);
68}
69
70uint8_t nicnatsemi_chip_readb(const chipaddr addr)
71{
72 OUTL(((uint32_t)addr & 0x0000FFFF), io_base_addr + BOOT_ROM_ADDR);
73 /*
74 * The datasheet requires 32 bit accesses to this register, but it seems
75 * that requirement might only apply if the register is memory mapped.
76 * Bit 8-31 of this register are apparently don't care, and if this
77 * register is I/O port mapped 8 bit accesses to the lowest byte of the
78 * register seem to work fine. Due to that, we ignore the advice in the
79 * data sheet.
80 */
81 return INB(io_base_addr + BOOT_ROM_DATA);
82}
83
84#else
85#error PCI port I/O access is not supported on this architecture yet.
86#endif