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Mark Marshall90021f22010-12-03 14:48:11 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Mark Marshall
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <stdlib.h>
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000021#include <strings.h>
Mark Marshall90021f22010-12-03 14:48:11 +000022#include <string.h>
23#include "flash.h"
24#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000025#include "hwaccess.h"
Mark Marshall90021f22010-12-03 14:48:11 +000026
27#define PCI_VENDOR_ID_OGP 0x1227
28
29/* These are the register addresses for the OGD1 / OGA1. If they are
30 * different for later versions of the hardware then we will need
31 * logic to select between the different hardware versions. */
32#define OGA1_XP10_BPROM_SI 0x0040 /* W */
33#define OGA1_XP10_BPROM_SO 0x0040 /* R */
34#define OGA1_XP10_BPROM_CE_BAR 0x0044 /* W */
35#define OGA1_XP10_BPROM_SCK 0x0048 /* W */
36#define OGA1_XP10_BPROM_REG_SEL 0x004C /* W */
37#define OGA1_XP10_CPROM_SI 0x0050 /* W */
38#define OGA1_XP10_CPROM_SO 0x0050 /* R */
39#define OGA1_XP10_CPROM_CE_BAR 0x0054 /* W */
40#define OGA1_XP10_CPROM_SCK 0x0058 /* W */
41#define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */
42
43static uint8_t *ogp_spibar;
44
45static uint32_t ogp_reg_sel;
46static uint32_t ogp_reg_siso;
47static uint32_t ogp_reg__ce;
48static uint32_t ogp_reg_sck;
49
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000050const struct dev_entry ogp_spi[] = {
Mark Marshall90021f22010-12-03 14:48:11 +000051 {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000052
53 {0},
Mark Marshall90021f22010-12-03 14:48:11 +000054};
55
56static void ogp_request_spibus(void)
57{
58 pci_mmio_writel(1, ogp_spibar + ogp_reg_sel);
59}
60
61static void ogp_release_spibus(void)
62{
63 pci_mmio_writel(0, ogp_spibar + ogp_reg_sel);
64}
65
66static void ogp_bitbang_set_cs(int val)
67{
68 pci_mmio_writel(val, ogp_spibar + ogp_reg__ce);
69}
70
71static void ogp_bitbang_set_sck(int val)
72{
73 pci_mmio_writel(val, ogp_spibar + ogp_reg_sck);
74}
75
76static void ogp_bitbang_set_mosi(int val)
77{
78 pci_mmio_writel(val, ogp_spibar + ogp_reg_siso);
79}
80
81static int ogp_bitbang_get_miso(void)
82{
83 uint32_t tmp;
84
85 tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso);
86 return tmp & 0x1;
87}
88
89static const struct bitbang_spi_master bitbang_spi_master_ogp = {
90 .type = BITBANG_SPI_MASTER_OGP,
91 .set_cs = ogp_bitbang_set_cs,
92 .set_sck = ogp_bitbang_set_sck,
93 .set_mosi = ogp_bitbang_set_mosi,
94 .get_miso = ogp_bitbang_get_miso,
95 .request_bus = ogp_request_spibus,
96 .release_bus = ogp_release_spibus,
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +000097 .half_period = 0,
Mark Marshall90021f22010-12-03 14:48:11 +000098};
99
100int ogp_spi_init(void)
101{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000102 struct pci_dev *dev = NULL;
Mark Marshall90021f22010-12-03 14:48:11 +0000103 char *type;
104
105 type = extract_programmer_param("rom");
106
107 if (!type) {
108 msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
109 "which flashchip you want to access.\n");
110 return 1;
111 } else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
112 ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
113 ogp_reg_siso = OGA1_XP10_BPROM_SI;
114 ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
115 ogp_reg_sck = OGA1_XP10_BPROM_SCK;
116 } else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
117 ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
118 ogp_reg_siso = OGA1_XP10_CPROM_SI;
119 ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
120 ogp_reg_sck = OGA1_XP10_CPROM_SCK;
121 } else {
122 msg_perr("Invalid or missing rom= parameter.\n");
123 return 1;
124 }
125
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000126 if (rget_io_perms())
127 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000128
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000129 dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
130 if (!dev)
131 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000132
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000133 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000134 if (!io_base_addr)
135 return 1;
136
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000137 ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
138 if (ogp_spibar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +0000139 return 1;
140
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000141 if (bitbang_spi_init(&bitbang_spi_master_ogp))
Mark Marshall90021f22010-12-03 14:48:11 +0000142 return 1;
143
Mark Marshall90021f22010-12-03 14:48:11 +0000144 return 0;
145}