blob: 2ed1dd0a8efcaa2a25eec560cec1b56f3b6cfa94 [file] [log] [blame]
Jason Wanga3f04be2008-11-28 21:36:51 +00001/*
2 * This file is part of the flashrom project.
3 *
Jason Wang13f98ce2008-11-29 15:07:15 +00004 * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang@amd.com>
5 * Copyright (C) 2008 Joe Bao <Zheng.Bao@amd.com>
Uwe Hermann97e8f222009-04-13 21:35:49 +00006 * Copyright (C) 2008 Advanced Micro Devices, Inc.
Jason Wanga3f04be2008-11-28 21:36:51 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <stdio.h>
24#include <string.h>
25#include <stdint.h>
26#include <sys/mman.h>
27#include <pci/pci.h>
28#include "flash.h"
29#include "spi.h"
30
31typedef struct _spi_controller {
32 unsigned int spi_cntrl0; /* 00h */
33 unsigned int restrictedcmd1; /* 04h */
34 unsigned int restrictedcmd2; /* 08h */
35 unsigned int spi_cntrl1; /* 0ch */
36 unsigned int spi_cmdvalue0; /* 10h */
37 unsigned int spi_cmdvalue1; /* 14h */
38 unsigned int spi_cmdvalue2; /* 18h */
39 unsigned int spi_fakeid; /* 1Ch */
40} sb600_spi_controller;
41
42sb600_spi_controller *spi_bar = NULL;
43uint8_t volatile *sb600_spibar;
44
45int sb600_spi_read(struct flashchip *flash, uint8_t *buf)
46{
47 int rc = 0, i;
48 int total_size = flash->total_size * 1024;
49 int page_size = 8;
50
51 for (i = 0; i < total_size / page_size; i++)
52 spi_nbyte_read(i * page_size, (void *)(buf + i * page_size),
53 page_size);
54 return rc;
55}
56
57uint8_t sb600_read_status_register(void)
58{
59 const unsigned char cmd[0x02] = { JEDEC_RDSR, 0x00 };
60 unsigned char readarr[JEDEC_RDSR_INSIZE];
61
62 /* Read Status Register */
63 spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
64 return readarr[0];
65}
66
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +000067int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf)
Jason Wanga3f04be2008-11-28 21:36:51 +000068{
69 int rc = 0, i;
70 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +000071 int result;
Jason Wanga3f04be2008-11-28 21:36:51 +000072
73 /* Erase first */
74 printf("Erasing flash before programming... ");
75 flash->erase(flash);
76 printf("done.\n");
77
78 printf("Programming flash");
79 for (i = 0; i < total_size; i++, buf++) {
80 spi_disable_blockprotect();
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +000081 result = spi_write_enable();
82 if (result)
83 return result;
Jason Wanga3f04be2008-11-28 21:36:51 +000084 spi_byte_program(i, *buf);
85 /* wait program complete. */
86 if (i % 0x8000 == 0)
87 printf(".");
88 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
89 ;
90 }
91 printf(" done.\n");
92 return rc;
93}
94
95void reset_internal_fifo_pointer(void)
96{
97 sb600_spibar[2] |= 0x10;
98
99 while (sb600_spibar[0xD] & 0x7)
100 printf("reset\n");
101}
102
103void execute_command(void)
104{
105 sb600_spibar[2] |= 1;
106
107 while (sb600_spibar[2] & 1)
108 ;
109}
110
111int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
112 const unsigned char *writearr, unsigned char *readarr)
113{
114 int count;
115 /* First byte is cmd which can not being sent through FIFO. */
116 unsigned char cmd = *writearr++;
117
118 writecnt--;
119
120 spi_bar = (sb600_spi_controller *) sb600_spibar;
121
122 printf_debug("%s, cmd=%x, writecnt=%x, readcnt=%x\n",
123 __func__, cmd, writecnt, readcnt);
124
125 if (readcnt > 8) {
126 printf("%s, SB600 SPI controller can not receive %d bytes, "
127 "which is limited with 8 bytes\n", __func__, readcnt);
128 return 1;
129 }
130
131 if (writecnt > 8) {
132 printf("%s, SB600 SPI controller can not sent %d bytes, "
133 "which is limited with 8 bytes\n", __func__, writecnt);
134 return 1;
135 }
136
137 sb600_spibar[0] = cmd;
138 sb600_spibar[1] = readcnt << 4 | (writecnt);
139
140 /* Before we use the FIFO, reset it first. */
141 reset_internal_fifo_pointer();
142
143 /* Send the write byte to FIFO. */
144 for (count = 0; count < writecnt; count++, writearr++) {
145 printf_debug(" [%x]", *writearr);
146 sb600_spibar[0xC] = *writearr;
147 }
148 printf_debug("\n");
149
150 /*
151 * We should send the data by sequence, which means we need to reset
152 * the FIFO pointer to the first byte we want to send.
153 */
154 reset_internal_fifo_pointer();
155
156 execute_command();
157
158 /*
159 * After the command executed, we should find out the index of the
160 * received byte. Here we just reset the FIFO pointer, skip the
161 * writecnt, is there anyone who have anther method to replace it?
162 */
163 reset_internal_fifo_pointer();
164
165 for (count = 0; count < writecnt; count++) {
166 cmd = sb600_spibar[0xC]; /* Skip the byte we send. */
167 printf_debug("[ %2x]", cmd);
168 }
169
170 printf_debug("The FIFO pointer 6 is %d.\n", sb600_spibar[0xd] & 0x07);
171 for (count = 0; count < readcnt; count++, readarr++) {
172 *readarr = sb600_spibar[0xC];
173 printf_debug("[%02x]", *readarr);
174 }
175 printf_debug("\n");
176
177 return 0;
178}