blob: 83ca20f96b1fb3dbbd890e0ea2010ea4ee897fcd [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the common SPI chip driver functions
23 */
24
25#include <string.h>
26#include "flash.h"
27#include "flashchips.h"
28#include "chipdrivers.h"
29#include "spi.h"
30
31void spi_prettyprint_status_register(struct flashchip *flash);
32
33static int spi_rdid(unsigned char *readarr, int bytes)
34{
35 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
36 int ret;
37 int i;
38
39 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
40 if (ret)
41 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000042 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000043 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000044 msg_cspew(" 0x%02x", readarr[i]);
45 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000046 return 0;
47}
48
49static int spi_rems(unsigned char *readarr)
50{
51 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
52 uint32_t readaddr;
53 int ret;
54
55 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
56 if (ret == SPI_INVALID_ADDRESS) {
57 /* Find the lowest even address allowed for reads. */
58 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
59 cmd[1] = (readaddr >> 16) & 0xff,
60 cmd[2] = (readaddr >> 8) & 0xff,
61 cmd[3] = (readaddr >> 0) & 0xff,
62 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
63 }
64 if (ret)
65 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000066 msg_cspew("REMS returned %02x %02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000067 return 0;
68}
69
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000070static int spi_res(unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000071{
72 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
73 uint32_t readaddr;
74 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000075 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000076
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000077 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000078 if (ret == SPI_INVALID_ADDRESS) {
79 /* Find the lowest even address allowed for reads. */
80 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
81 cmd[1] = (readaddr >> 16) & 0xff,
82 cmd[2] = (readaddr >> 8) & 0xff,
83 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000084 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000085 }
86 if (ret)
87 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000088 msg_cspew("RES returned");
89 for (i = 0; i < bytes; i++)
90 msg_cspew(" 0x%02x", readarr[i]);
91 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000092 return 0;
93}
94
95int spi_write_enable(void)
96{
97 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
98 int result;
99
100 /* Send WREN (Write Enable) */
101 result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
102
103 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000104 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000105
106 return result;
107}
108
109int spi_write_disable(void)
110{
111 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
112
113 /* Send WRDI (Write Disable) */
114 return spi_send_command(sizeof(cmd), 0, cmd, NULL);
115}
116
117static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
118{
119 unsigned char readarr[4];
120 uint32_t id1;
121 uint32_t id2;
122
123 if (spi_rdid(readarr, bytes))
124 return 0;
125
126 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000127 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000128
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000129 /* Check if this is a continuation vendor ID.
130 * FIXME: Handle continuation device IDs.
131 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000132 if (readarr[0] == 0x7f) {
133 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000134 msg_cdbg("RDID byte 1 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000135 id1 = (readarr[0] << 8) | readarr[1];
136 id2 = readarr[2];
137 if (bytes > 3) {
138 id2 <<= 8;
139 id2 |= readarr[3];
140 }
141 } else {
142 id1 = readarr[0];
143 id2 = (readarr[1] << 8) | readarr[2];
144 }
145
Sean Nelsoned479d22010-03-24 23:14:32 +0000146 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000147
148 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
149 /* Print the status register to tell the
150 * user about possible write protection.
151 */
152 spi_prettyprint_status_register(flash);
153
154 return 1;
155 }
156
157 /* Test if this is a pure vendor match. */
158 if (id1 == flash->manufacture_id &&
159 GENERIC_DEVICE_ID == flash->model_id)
160 return 1;
161
162 /* Test if there is any vendor ID. */
163 if (GENERIC_MANUF_ID == flash->manufacture_id &&
164 id1 != 0xff)
165 return 1;
166
167 return 0;
168}
169
170int probe_spi_rdid(struct flashchip *flash)
171{
172 return probe_spi_rdid_generic(flash, 3);
173}
174
Sean Nelson14ba6682010-02-26 05:48:29 +0000175int probe_spi_rdid4(struct flashchip *flash)
176{
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000177 /* Some SPI controllers do not support commands with writecnt=1 and
178 * readcnt=4.
179 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000180 switch (spi_controller) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000181#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000182#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000183 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +0000184 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000185 msg_cinfo("4 byte RDID not supported on this SPI controller\n");
186 return 0;
187 break;
Sean Nelson14ba6682010-02-26 05:48:29 +0000188#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000189#endif
Sean Nelson14ba6682010-02-26 05:48:29 +0000190 default:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000191 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000192 }
193
194 return 0;
195}
196
197int probe_spi_rems(struct flashchip *flash)
198{
199 unsigned char readarr[JEDEC_REMS_INSIZE];
200 uint32_t id1, id2;
201
202 if (spi_rems(readarr))
203 return 0;
204
205 id1 = readarr[0];
206 id2 = readarr[1];
207
Sean Nelsoned479d22010-03-24 23:14:32 +0000208 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000209
210 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
211 /* Print the status register to tell the
212 * user about possible write protection.
213 */
214 spi_prettyprint_status_register(flash);
215
216 return 1;
217 }
218
219 /* Test if this is a pure vendor match. */
220 if (id1 == flash->manufacture_id &&
221 GENERIC_DEVICE_ID == flash->model_id)
222 return 1;
223
224 /* Test if there is any vendor ID. */
225 if (GENERIC_MANUF_ID == flash->manufacture_id &&
226 id1 != 0xff)
227 return 1;
228
229 return 0;
230}
231
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000232int probe_spi_res1(struct flashchip *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000233{
234 unsigned char readarr[3];
235 uint32_t id2;
236 const unsigned char allff[] = {0xff, 0xff, 0xff};
237 const unsigned char all00[] = {0x00, 0x00, 0x00};
238
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000239 /* We only want one-byte RES if RDID and REMS are unusable. */
240
Sean Nelson14ba6682010-02-26 05:48:29 +0000241 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
242 * 0x00 0x00 0x00. In that case, RES is pointless.
243 */
244 if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) &&
245 memcmp(readarr, all00, 3)) {
246 msg_cdbg("Ignoring RES in favour of RDID.\n");
247 return 0;
248 }
249 /* Check if REMS is usable and does not return 0xff 0xff or
250 * 0x00 0x00. In that case, RES is pointless.
251 */
252 if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
253 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
254 msg_cdbg("Ignoring RES in favour of REMS.\n");
255 return 0;
256 }
257
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000258 if (spi_res(readarr, 1))
Sean Nelson14ba6682010-02-26 05:48:29 +0000259 return 0;
260
Sean Nelson14ba6682010-02-26 05:48:29 +0000261 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000262
Sean Nelsoned479d22010-03-24 23:14:32 +0000263 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000264
Sean Nelson14ba6682010-02-26 05:48:29 +0000265 if (id2 != flash->model_id)
266 return 0;
267
268 /* Print the status register to tell the
269 * user about possible write protection.
270 */
271 spi_prettyprint_status_register(flash);
272 return 1;
273}
274
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000275int probe_spi_res2(struct flashchip *flash)
276{
277 unsigned char readarr[2];
278 uint32_t id1, id2;
279
280 if (spi_res(readarr, 2))
281 return 0;
282
283 id1 = readarr[0];
284 id2 = readarr[1];
285
286 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
287
288 if (id1 != flash->manufacture_id || id2 != flash->model_id)
289 return 0;
290
291 /* Print the status register to tell the
292 * user about possible write protection.
293 */
294 spi_prettyprint_status_register(flash);
295 return 1;
296}
297
Sean Nelson14ba6682010-02-26 05:48:29 +0000298uint8_t spi_read_status_register(void)
299{
300 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
301 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
302 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
303 int ret;
304
305 /* Read Status Register */
306 ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
307 if (ret)
Sean Nelsoned479d22010-03-24 23:14:32 +0000308 msg_cerr("RDSR failed!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000309
310 return readarr[0];
311}
312
313/* Prettyprint the status register. Common definitions. */
314void spi_prettyprint_status_register_common(uint8_t status)
315{
Sean Nelsoned479d22010-03-24 23:14:32 +0000316 msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000317 "%sset\n", (status & (1 << 5)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000318 msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000319 "%sset\n", (status & (1 << 4)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000320 msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000321 "%sset\n", (status & (1 << 3)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000322 msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000323 "%sset\n", (status & (1 << 2)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000324 msg_cdbg("Chip status register: Write Enable Latch (WEL) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000325 "%sset\n", (status & (1 << 1)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000326 msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000327 "%sset\n", (status & (1 << 0)) ? "" : "not ");
328}
329
330/* Prettyprint the status register. Works for
331 * ST M25P series
332 * MX MX25L series
333 */
334void spi_prettyprint_status_register_st_m25p(uint8_t status)
335{
Sean Nelsoned479d22010-03-24 23:14:32 +0000336 msg_cdbg("Chip status register: Status Register Write Disable "
Sean Nelson14ba6682010-02-26 05:48:29 +0000337 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000338 msg_cdbg("Chip status register: Bit 6 is "
Sean Nelson14ba6682010-02-26 05:48:29 +0000339 "%sset\n", (status & (1 << 6)) ? "" : "not ");
340 spi_prettyprint_status_register_common(status);
341}
342
343void spi_prettyprint_status_register_sst25(uint8_t status)
344{
Sean Nelsoned479d22010-03-24 23:14:32 +0000345 msg_cdbg("Chip status register: Block Protect Write Disable "
Sean Nelson14ba6682010-02-26 05:48:29 +0000346 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Sean Nelsoned479d22010-03-24 23:14:32 +0000347 msg_cdbg("Chip status register: Auto Address Increment Programming "
Sean Nelson14ba6682010-02-26 05:48:29 +0000348 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
349 spi_prettyprint_status_register_common(status);
350}
351
352/* Prettyprint the status register. Works for
353 * SST 25VF016
354 */
355void spi_prettyprint_status_register_sst25vf016(uint8_t status)
356{
357 const char *bpt[] = {
358 "none",
359 "1F0000H-1FFFFFH",
360 "1E0000H-1FFFFFH",
361 "1C0000H-1FFFFFH",
362 "180000H-1FFFFFH",
363 "100000H-1FFFFFH",
364 "all", "all"
365 };
366 spi_prettyprint_status_register_sst25(status);
Sean Nelsoned479d22010-03-24 23:14:32 +0000367 msg_cdbg("Resulting block protection : %s\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000368 bpt[(status & 0x1c) >> 2]);
369}
370
371void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
372{
373 const char *bpt[] = {
374 "none",
375 "0x70000-0x7ffff",
376 "0x60000-0x7ffff",
377 "0x40000-0x7ffff",
378 "all blocks", "all blocks", "all blocks", "all blocks"
379 };
380 spi_prettyprint_status_register_sst25(status);
Sean Nelsoned479d22010-03-24 23:14:32 +0000381 msg_cdbg("Resulting block protection : %s\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000382 bpt[(status & 0x1c) >> 2]);
383}
384
385void spi_prettyprint_status_register(struct flashchip *flash)
386{
387 uint8_t status;
388
389 status = spi_read_status_register();
Sean Nelsoned479d22010-03-24 23:14:32 +0000390 msg_cdbg("Chip status register is %02x\n", status);
Sean Nelson14ba6682010-02-26 05:48:29 +0000391 switch (flash->manufacture_id) {
392 case ST_ID:
393 if (((flash->model_id & 0xff00) == 0x2000) ||
394 ((flash->model_id & 0xff00) == 0x2500))
395 spi_prettyprint_status_register_st_m25p(status);
396 break;
397 case MX_ID:
398 if ((flash->model_id & 0xff00) == 0x2000)
399 spi_prettyprint_status_register_st_m25p(status);
400 break;
401 case SST_ID:
402 switch (flash->model_id) {
403 case 0x2541:
404 spi_prettyprint_status_register_sst25vf016(status);
405 break;
406 case 0x8d:
407 case 0x258d:
408 spi_prettyprint_status_register_sst25vf040b(status);
409 break;
410 default:
411 spi_prettyprint_status_register_sst25(status);
412 break;
413 }
414 break;
415 }
416}
417
418int spi_chip_erase_60(struct flashchip *flash)
419{
420 int result;
421 struct spi_command cmds[] = {
422 {
423 .writecnt = JEDEC_WREN_OUTSIZE,
424 .writearr = (const unsigned char[]){ JEDEC_WREN },
425 .readcnt = 0,
426 .readarr = NULL,
427 }, {
428 .writecnt = JEDEC_CE_60_OUTSIZE,
429 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
430 .readcnt = 0,
431 .readarr = NULL,
432 }, {
433 .writecnt = 0,
434 .writearr = NULL,
435 .readcnt = 0,
436 .readarr = NULL,
437 }};
438
439 result = spi_disable_blockprotect();
440 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000441 msg_cerr("spi_disable_blockprotect failed\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000442 return result;
443 }
444
445 result = spi_send_multicommand(cmds);
446 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000447 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000448 __func__);
449 return result;
450 }
451 /* Wait until the Write-In-Progress bit is cleared.
452 * This usually takes 1-85 s, so wait in 1 s steps.
453 */
454 /* FIXME: We assume spi_read_status_register will never fail. */
455 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
456 programmer_delay(1000 * 1000);
457 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000458 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000459 return -1;
460 }
461 return 0;
462}
463
464int spi_chip_erase_c7(struct flashchip *flash)
465{
466 int result;
467 struct spi_command cmds[] = {
468 {
469 .writecnt = JEDEC_WREN_OUTSIZE,
470 .writearr = (const unsigned char[]){ JEDEC_WREN },
471 .readcnt = 0,
472 .readarr = NULL,
473 }, {
474 .writecnt = JEDEC_CE_C7_OUTSIZE,
475 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
476 .readcnt = 0,
477 .readarr = NULL,
478 }, {
479 .writecnt = 0,
480 .writearr = NULL,
481 .readcnt = 0,
482 .readarr = NULL,
483 }};
484
485 result = spi_disable_blockprotect();
486 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000487 msg_cerr("spi_disable_blockprotect failed\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000488 return result;
489 }
490
491 result = spi_send_multicommand(cmds);
492 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000493 msg_cerr("%s failed during command execution\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000494 return result;
495 }
496 /* Wait until the Write-In-Progress bit is cleared.
497 * This usually takes 1-85 s, so wait in 1 s steps.
498 */
499 /* FIXME: We assume spi_read_status_register will never fail. */
500 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
501 programmer_delay(1000 * 1000);
502 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000503 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000504 return -1;
505 }
506 return 0;
507}
508
Sean Nelson14ba6682010-02-26 05:48:29 +0000509int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
510{
511 int result;
512 struct spi_command cmds[] = {
513 {
514 .writecnt = JEDEC_WREN_OUTSIZE,
515 .writearr = (const unsigned char[]){ JEDEC_WREN },
516 .readcnt = 0,
517 .readarr = NULL,
518 }, {
519 .writecnt = JEDEC_BE_52_OUTSIZE,
520 .writearr = (const unsigned char[]){
521 JEDEC_BE_52,
522 (addr >> 16) & 0xff,
523 (addr >> 8) & 0xff,
524 (addr & 0xff)
525 },
526 .readcnt = 0,
527 .readarr = NULL,
528 }, {
529 .writecnt = 0,
530 .writearr = NULL,
531 .readcnt = 0,
532 .readarr = NULL,
533 }};
534
535 result = spi_send_multicommand(cmds);
536 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000537 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000538 __func__, addr);
539 return result;
540 }
541 /* Wait until the Write-In-Progress bit is cleared.
542 * This usually takes 100-4000 ms, so wait in 100 ms steps.
543 */
544 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
545 programmer_delay(100 * 1000);
546 if (check_erased_range(flash, addr, blocklen)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000547 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000548 return -1;
549 }
550 return 0;
551}
552
553/* Block size is usually
554 * 64k for Macronix
555 * 32k for SST
556 * 4-32k non-uniform for EON
557 */
558int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
559{
560 int result;
561 struct spi_command cmds[] = {
562 {
563 .writecnt = JEDEC_WREN_OUTSIZE,
564 .writearr = (const unsigned char[]){ JEDEC_WREN },
565 .readcnt = 0,
566 .readarr = NULL,
567 }, {
568 .writecnt = JEDEC_BE_D8_OUTSIZE,
569 .writearr = (const unsigned char[]){
570 JEDEC_BE_D8,
571 (addr >> 16) & 0xff,
572 (addr >> 8) & 0xff,
573 (addr & 0xff)
574 },
575 .readcnt = 0,
576 .readarr = NULL,
577 }, {
578 .writecnt = 0,
579 .writearr = NULL,
580 .readcnt = 0,
581 .readarr = NULL,
582 }};
583
584 result = spi_send_multicommand(cmds);
585 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000586 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000587 __func__, addr);
588 return result;
589 }
590 /* Wait until the Write-In-Progress bit is cleared.
591 * This usually takes 100-4000 ms, so wait in 100 ms steps.
592 */
593 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
594 programmer_delay(100 * 1000);
595 if (check_erased_range(flash, addr, blocklen)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000596 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000597 return -1;
598 }
599 return 0;
600}
601
602/* Block size is usually
603 * 4k for PMC
604 */
605int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
606{
607 int result;
608 struct spi_command cmds[] = {
609 {
610 .writecnt = JEDEC_WREN_OUTSIZE,
611 .writearr = (const unsigned char[]){ JEDEC_WREN },
612 .readcnt = 0,
613 .readarr = NULL,
614 }, {
615 .writecnt = JEDEC_BE_D7_OUTSIZE,
616 .writearr = (const unsigned char[]){
617 JEDEC_BE_D7,
618 (addr >> 16) & 0xff,
619 (addr >> 8) & 0xff,
620 (addr & 0xff)
621 },
622 .readcnt = 0,
623 .readarr = NULL,
624 }, {
625 .writecnt = 0,
626 .writearr = NULL,
627 .readcnt = 0,
628 .readarr = NULL,
629 }};
630
631 result = spi_send_multicommand(cmds);
632 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000633 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000634 __func__, addr);
635 return result;
636 }
637 /* Wait until the Write-In-Progress bit is cleared.
638 * This usually takes 100-4000 ms, so wait in 100 ms steps.
639 */
640 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
641 programmer_delay(100 * 1000);
642 if (check_erased_range(flash, addr, blocklen)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000643 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000644 return -1;
645 }
646 return 0;
647}
648
649int spi_chip_erase_d8(struct flashchip *flash)
650{
651 int i, rc = 0;
652 int total_size = flash->total_size * 1024;
653 int erase_size = 64 * 1024;
654
655 spi_disable_blockprotect();
656
Sean Nelsoned479d22010-03-24 23:14:32 +0000657 msg_cinfo("Erasing chip: \n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000658
659 for (i = 0; i < total_size / erase_size; i++) {
660 rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
661 if (rc) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000662 msg_cerr("Error erasing block at 0x%x\n", i);
Sean Nelson14ba6682010-02-26 05:48:29 +0000663 break;
664 }
665 }
666
Sean Nelsoned479d22010-03-24 23:14:32 +0000667 msg_cinfo("\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000668
669 return rc;
670}
671
672/* Sector size is usually 4k, though Macronix eliteflash has 64k */
673int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
674{
675 int result;
676 struct spi_command cmds[] = {
677 {
678 .writecnt = JEDEC_WREN_OUTSIZE,
679 .writearr = (const unsigned char[]){ JEDEC_WREN },
680 .readcnt = 0,
681 .readarr = NULL,
682 }, {
683 .writecnt = JEDEC_SE_OUTSIZE,
684 .writearr = (const unsigned char[]){
685 JEDEC_SE,
686 (addr >> 16) & 0xff,
687 (addr >> 8) & 0xff,
688 (addr & 0xff)
689 },
690 .readcnt = 0,
691 .readarr = NULL,
692 }, {
693 .writecnt = 0,
694 .writearr = NULL,
695 .readcnt = 0,
696 .readarr = NULL,
697 }};
698
699 result = spi_send_multicommand(cmds);
700 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000701 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000702 __func__, addr);
703 return result;
704 }
705 /* Wait until the Write-In-Progress bit is cleared.
706 * This usually takes 15-800 ms, so wait in 10 ms steps.
707 */
708 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
709 programmer_delay(10 * 1000);
710 if (check_erased_range(flash, addr, blocklen)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000711 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000712 return -1;
713 }
714 return 0;
715}
716
717int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
718{
719 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000720 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000721 __func__);
722 return -1;
723 }
724 return spi_chip_erase_60(flash);
725}
726
727int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
728{
729 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000730 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000731 __func__);
732 return -1;
733 }
734 return spi_chip_erase_c7(flash);
735}
736
737int spi_write_status_enable(void)
738{
739 const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
740 int result;
741
742 /* Send EWSR (Enable Write Status Register). */
743 result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
744
745 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000746 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000747
748 return result;
749}
750
751/*
752 * This is according the SST25VF016 datasheet, who knows it is more
753 * generic that this...
754 */
755int spi_write_status_register(int status)
756{
757 int result;
758 struct spi_command cmds[] = {
759 {
760 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
761 .writecnt = JEDEC_EWSR_OUTSIZE,
762 .writearr = (const unsigned char[]){ JEDEC_EWSR },
763 .readcnt = 0,
764 .readarr = NULL,
765 }, {
766 .writecnt = JEDEC_WRSR_OUTSIZE,
767 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
768 .readcnt = 0,
769 .readarr = NULL,
770 }, {
771 .writecnt = 0,
772 .writearr = NULL,
773 .readcnt = 0,
774 .readarr = NULL,
775 }};
776
777 result = spi_send_multicommand(cmds);
778 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000779 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000780 __func__);
781 }
782 return result;
783}
784
785int spi_byte_program(int addr, uint8_t databyte)
786{
787 int result;
788 struct spi_command cmds[] = {
789 {
790 .writecnt = JEDEC_WREN_OUTSIZE,
791 .writearr = (const unsigned char[]){ JEDEC_WREN },
792 .readcnt = 0,
793 .readarr = NULL,
794 }, {
795 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
796 .writearr = (const unsigned char[]){
797 JEDEC_BYTE_PROGRAM,
798 (addr >> 16) & 0xff,
799 (addr >> 8) & 0xff,
800 (addr & 0xff),
801 databyte
802 },
803 .readcnt = 0,
804 .readarr = NULL,
805 }, {
806 .writecnt = 0,
807 .writearr = NULL,
808 .readcnt = 0,
809 .readarr = NULL,
810 }};
811
812 result = spi_send_multicommand(cmds);
813 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000814 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000815 __func__, addr);
816 }
817 return result;
818}
819
820int spi_nbyte_program(int addr, uint8_t *bytes, int len)
821{
822 int result;
823 /* FIXME: Switch to malloc based on len unless that kills speed. */
824 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
825 JEDEC_BYTE_PROGRAM,
826 (addr >> 16) & 0xff,
827 (addr >> 8) & 0xff,
828 (addr >> 0) & 0xff,
829 };
830 struct spi_command cmds[] = {
831 {
832 .writecnt = JEDEC_WREN_OUTSIZE,
833 .writearr = (const unsigned char[]){ JEDEC_WREN },
834 .readcnt = 0,
835 .readarr = NULL,
836 }, {
837 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
838 .writearr = cmd,
839 .readcnt = 0,
840 .readarr = NULL,
841 }, {
842 .writecnt = 0,
843 .writearr = NULL,
844 .readcnt = 0,
845 .readarr = NULL,
846 }};
847
848 if (!len) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000849 msg_cerr("%s called for zero-length write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000850 return 1;
851 }
852 if (len > 256) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000853 msg_cerr("%s called for too long a write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000854 return 1;
855 }
856
857 memcpy(&cmd[4], bytes, len);
858
859 result = spi_send_multicommand(cmds);
860 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000861 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000862 __func__, addr);
863 }
864 return result;
865}
866
867int spi_disable_blockprotect(void)
868{
869 uint8_t status;
870 int result;
871
872 status = spi_read_status_register();
873 /* If there is block protection in effect, unprotect it first. */
874 if ((status & 0x3c) != 0) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000875 msg_cdbg("Some block protection in effect, disabling\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000876 result = spi_write_status_register(status & ~0x3c);
877 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000878 msg_cerr("spi_write_status_register failed\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000879 return result;
880 }
881 }
882 return 0;
883}
884
885int spi_nbyte_read(int address, uint8_t *bytes, int len)
886{
887 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
888 JEDEC_READ,
889 (address >> 16) & 0xff,
890 (address >> 8) & 0xff,
891 (address >> 0) & 0xff,
892 };
893
894 /* Send Read */
895 return spi_send_command(sizeof(cmd), len, cmd, bytes);
896}
897
898/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000899 * Read a part of the flash chip.
Sean Nelson14ba6682010-02-26 05:48:29 +0000900 * Each page is read separately in chunks with a maximum size of chunksize.
901 */
902int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
903{
904 int rc = 0;
905 int i, j, starthere, lenhere;
906 int page_size = flash->page_size;
907 int toread;
908
909 /* Warning: This loop has a very unusual condition and body.
910 * The loop needs to go through each page with at least one affected
911 * byte. The lowest page number is (start / page_size) since that
912 * division rounds down. The highest page number we want is the page
913 * where the last byte of the range lives. That last byte has the
914 * address (start + len - 1), thus the highest page number is
915 * (start + len - 1) / page_size. Since we want to include that last
916 * page as well, the loop condition uses <=.
917 */
918 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
919 /* Byte position of the first byte in the range in this page. */
920 /* starthere is an offset to the base address of the chip. */
921 starthere = max(start, i * page_size);
922 /* Length of bytes in the range in this page. */
923 lenhere = min(start + len, (i + 1) * page_size) - starthere;
924 for (j = 0; j < lenhere; j += chunksize) {
925 toread = min(chunksize, lenhere - j);
926 rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
927 if (rc)
928 break;
929 }
930 if (rc)
931 break;
932 }
933
934 return rc;
935}
936
937/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000938 * Write a part of the flash chip.
939 * Each page is written separately in chunks with a maximum size of chunksize.
940 */
941int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
942{
943 int rc = 0;
944 int i, j, starthere, lenhere;
945 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
946 * in struct flashchip to do this properly. All chips using
947 * spi_chip_write_256 have page_size set to max_writechunk_size, so
948 * we're OK for now.
949 */
950 int page_size = flash->page_size;
951 int towrite;
952
953 /* Warning: This loop has a very unusual condition and body.
954 * The loop needs to go through each page with at least one affected
955 * byte. The lowest page number is (start / page_size) since that
956 * division rounds down. The highest page number we want is the page
957 * where the last byte of the range lives. That last byte has the
958 * address (start + len - 1), thus the highest page number is
959 * (start + len - 1) / page_size. Since we want to include that last
960 * page as well, the loop condition uses <=.
961 */
962 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
963 /* Byte position of the first byte in the range in this page. */
964 /* starthere is an offset to the base address of the chip. */
965 starthere = max(start, i * page_size);
966 /* Length of bytes in the range in this page. */
967 lenhere = min(start + len, (i + 1) * page_size) - starthere;
968 for (j = 0; j < lenhere; j += chunksize) {
969 towrite = min(chunksize, lenhere - j);
970 rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite);
971 if (rc)
972 break;
973 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
974 programmer_delay(10);
975 }
976 if (rc)
977 break;
978 }
979
980 return rc;
981}
982
983/*
Sean Nelson14ba6682010-02-26 05:48:29 +0000984 * Program chip using byte programming. (SLOW!)
985 * This is for chips which can only handle one byte writes
986 * and for chips where memory mapped programming is impossible
987 * (e.g. due to size constraints in IT87* for over 512 kB)
988 */
989int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
990{
991 int total_size = 1024 * flash->total_size;
992 int i, result = 0;
993
994 spi_disable_blockprotect();
995 /* Erase first */
Sean Nelsoned479d22010-03-24 23:14:32 +0000996 msg_cinfo("Erasing flash before programming... ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000997 if (erase_flash(flash)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000998 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +0000999 return -1;
1000 }
Sean Nelsoned479d22010-03-24 23:14:32 +00001001 msg_cinfo("done.\n");
Sean Nelson14ba6682010-02-26 05:48:29 +00001002 for (i = 0; i < total_size; i++) {
1003 result = spi_byte_program(i, buf[i]);
1004 if (result)
1005 return 1;
1006 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1007 programmer_delay(10);
1008 }
1009
1010 return 0;
1011}
1012
1013int spi_aai_write(struct flashchip *flash, uint8_t *buf)
1014{
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001015 uint32_t addr = 0;
1016 uint32_t len = flash->total_size * 1024;
1017 uint32_t pos = addr;
Sean Nelson14ba6682010-02-26 05:48:29 +00001018 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001019 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
1020 JEDEC_AAI_WORD_PROGRAM,
1021 };
1022 struct spi_command cmds[] = {
1023 {
1024 .writecnt = JEDEC_WREN_OUTSIZE,
1025 .writearr = (const unsigned char[]){ JEDEC_WREN },
1026 .readcnt = 0,
1027 .readarr = NULL,
1028 }, {
1029 .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE,
1030 .writearr = (const unsigned char[]){
1031 JEDEC_AAI_WORD_PROGRAM,
1032 (pos >> 16) & 0xff,
1033 (pos >> 8) & 0xff,
1034 (pos & 0xff),
1035 buf[0],
1036 buf[1]
1037 },
1038 .readcnt = 0,
1039 .readarr = NULL,
1040 }, {
1041 .writecnt = 0,
1042 .writearr = NULL,
1043 .readcnt = 0,
1044 .readarr = NULL,
1045 }};
Sean Nelson14ba6682010-02-26 05:48:29 +00001046
1047 switch (spi_controller) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +00001048#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001049#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001050 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +00001051 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001052 msg_cerr("%s: impossible with this SPI controller,"
Sean Nelson14ba6682010-02-26 05:48:29 +00001053 " degrading to byte program\n", __func__);
1054 return spi_chip_write_1(flash, buf);
1055#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001056#endif
Sean Nelson14ba6682010-02-26 05:48:29 +00001057 default:
1058 break;
1059 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001060
1061 /* The data sheet requires a start address with the low bit cleared. */
1062 if (addr % 2) {
1063 msg_cerr("%s: start address not even! Please report a bug at "
1064 "flashrom@flashrom.org\n", __func__);
1065 return SPI_GENERIC_ERROR;
1066 }
1067 /* The data sheet requires total AAI write length to be even. */
1068 if (len % 2) {
1069 msg_cerr("%s: total write length not even! Please report a "
1070 "bug at flashrom@flashrom.org\n", __func__);
1071 return SPI_GENERIC_ERROR;
1072 }
1073
Sean Nelson14ba6682010-02-26 05:48:29 +00001074 if (erase_flash(flash)) {
Sean Nelsoned479d22010-03-24 23:14:32 +00001075 msg_cerr("ERASE FAILED!\n");
Sean Nelson14ba6682010-02-26 05:48:29 +00001076 return -1;
1077 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001078
1079 result = spi_send_multicommand(cmds);
1080 if (result) {
1081 msg_cerr("%s failed during start command execution\n",
1082 __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +00001083 return result;
Sean Nelson14ba6682010-02-26 05:48:29 +00001084 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001085 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1086 programmer_delay(10);
1087
1088 /* We already wrote 2 bytes in the multicommand step. */
1089 pos += 2;
1090
1091 while (pos < addr + len) {
1092 cmd[1] = buf[pos++];
1093 cmd[2] = buf[pos++];
1094 spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
1095 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
1096 programmer_delay(10);
1097 }
1098
1099 /* Use WRDI to exit AAI mode. */
Sean Nelson14ba6682010-02-26 05:48:29 +00001100 spi_write_disable();
1101 return 0;
1102}