blob: db4d28f013ab00abbf264c041c22315c0eedda38 [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
Stefan Tauner1e146392011-09-15 23:52:55 +000022#ifndef __ICH_DESCRIPTORS_H__
23#define __ICH_DESCRIPTORS_H__ 1
24
Nico Huber4d440a72017-08-15 11:26:48 +020025#include <sys/types.h>
Stefan Tauner1e146392011-09-15 23:52:55 +000026#include <stdint.h>
Stefan Taunera8d838d2011-11-06 23:51:09 +000027#include "programmer.h" /* for enum ich_chipset */
Stefan Tauner1e146392011-09-15 23:52:55 +000028
29/* FIXME: Replace with generic return codes */
30#define ICH_RET_OK 0
31#define ICH_RET_ERR -1
32#define ICH_RET_WARN -2
33#define ICH_RET_PARAM -3
34#define ICH_RET_OOB -4
35
36#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */
Nico Huberd54e4f42017-03-23 23:45:47 +010037#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000038 /* 0-1: reserved */
39#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */
40#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF)
41#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */
42#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF)
43 /* 15-31: reserved */
44
45#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */
Nico Huberd54e4f42017-03-23 23:45:47 +010046#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000047
48/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
49 * descriptor are equal therefore they all share the same macros below. */
50#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */
51#define VSCC_BES (0x3 << VSCC_BES_OFF)
52#define VSCC_WG_OFF 2 /* 2: Write Granularity */
53#define VSCC_WG (0x1 << VSCC_WG_OFF)
54#define VSCC_WSR_OFF 3 /* 3: Write Status Required */
55#define VSCC_WSR (0x1 << VSCC_WSR_OFF)
56#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */
57#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF)
58 /* 5-7: reserved */
59#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */
60#define VSCC_EO (0xff << VSCC_EO_OFF)
61 /* 16-22: reserved */
62#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */
63#define VSCC_VCL (0x1 << VSCC_VCL_OFF)
64 /* 24-31: reserved */
65
Nico Huberfa622942017-03-24 17:25:37 +010066#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x07fff000)
67#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x07fff000) | 0x00000fff)
Stefan Tauner1e146392011-09-15 23:52:55 +000068
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000069void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl);
Stefan Tauner1e146392011-09-15 23:52:55 +000070
71struct ich_desc_content {
72 uint32_t FLVALSIG; /* 0x00 */
73 union { /* 0x04 */
74 uint32_t FLMAP0;
75 struct {
76 uint32_t FCBA :8, /* Flash Component Base Address */
77 NC :2, /* Number Of Components */
78 :6,
79 FRBA :8, /* Flash Region Base Address */
Nico Huberfa622942017-03-24 17:25:37 +010080 NR :3, /* Number Of Regions (reserved from Skylake on) */
Stefan Tauner1e146392011-09-15 23:52:55 +000081 :5;
82 };
83 };
84 union { /* 0x08 */
85 uint32_t FLMAP1;
86 struct {
87 uint32_t FMBA :8, /* Flash Master Base Address */
88 NM :3, /* Number Of Masters */
89 :5,
90 FISBA :8, /* Flash ICH Strap Base Address */
91 ISL :8; /* ICH Strap Length */
92 };
93 };
94 union { /* 0x0c */
95 uint32_t FLMAP2;
96 struct {
Nico Huber1dc3d422017-06-17 00:09:31 +020097 uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
98 MSL :8, /* MCH Strap Length */
99 ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */
100 RIL :8; /* Register Init Length (new since Hawell) */
Stefan Tauner1e146392011-09-15 23:52:55 +0000101 };
102 };
103};
104
105struct ich_desc_component {
106 union { /* 0x00 */
107 uint32_t FLCOMP; /* Flash Components Register */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000108 /* FLCOMP encoding on various generations:
109 *
110 * Chipset/Generation max_speed dual_output density
111 * [MHz] bits max. bits
112 * ICH8: 33 N/A 5 0:2, 3:5
113 * ICH9: 33 N/A 5 0:2, 3:5
114 * ICH10: 33 N/A 5 0:2, 3:5
115 * Ibex Peak/5: 50 N/A 5 0:2, 3:5
116 * Cougar Point/6: 50 30 5 0:2, 3:5
117 * Patsburg: 50 30 5 0:2, 3:5
118 * Panther Point/7 50 30 5 0:2, 3:5
119 * Lynx Point/8: 50 30 7 0:3, 4:7
Nico Huberfa622942017-03-24 17:25:37 +0100120 * Wildcat Point/9: 50 30 (multi I/O) 7 0:3, 4:7
121 * Sunrise Point/100: 48 30 7 0:3, 4:7
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000122 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000123 struct {
Duncan Laurie823096e2014-08-20 15:39:38 +0000124 uint32_t :17,
Stefan Tauner1e146392011-09-15 23:52:55 +0000125 freq_read :3,
126 fastread :1,
127 freq_fastread :3,
128 freq_write :3,
129 freq_read_id :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000130 dual_output :1, /* new since Cougar Point/6 */
131 :1;
132 } modes;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000133 struct {
134 uint32_t comp1_density :3,
135 comp2_density :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000136 :26;
137 } dens_old;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000138 struct {
139 uint32_t comp1_density :4, /* new since Lynx Point/8 */
140 comp2_density :4,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000141 :24;
142 } dens_new;
Stefan Tauner1e146392011-09-15 23:52:55 +0000143 };
144 union { /* 0x04 */
145 uint32_t FLILL; /* Flash Invalid Instructions Register */
146 struct {
147 uint32_t invalid_instr0 :8,
148 invalid_instr1 :8,
149 invalid_instr2 :8,
150 invalid_instr3 :8;
151 };
152 };
153 union { /* 0x08 */
Nico Huberfa622942017-03-24 17:25:37 +0100154 uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000155 struct {
156 uint32_t FPBA :13, /* Flash Partition Boundary Addr */
157 :19;
158 };
Nico Huberfa622942017-03-24 17:25:37 +0100159 uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000160 struct {
Nico Huberfa622942017-03-24 17:25:37 +0100161 uint32_t invalid_instr4 :8,
162 invalid_instr5 :8,
163 invalid_instr6 :8,
164 invalid_instr7 :8;
Stefan Tauner1e146392011-09-15 23:52:55 +0000165 };
166 };
167};
168
David Hendricks8e762302017-08-09 22:21:31 -0700169#define MAX_NUM_FLREGS 16
Nico Huberfa622942017-03-24 17:25:37 +0100170struct ich_desc_region {
171 /*
172 * Number of entries and width differ on various generations:
173 *
174 * Chipset/Generation #FLREGs width (bits)
175 * ICH8 .. Panther Point/7 5 13
176 * Lynx Point/8 .. Wildcat Point/9 7 15
177 * Sunrise Point/100 .. 10 15
David Hendricks8e762302017-08-09 22:21:31 -0700178 * Lewisburg/100 .. 16 15
Nico Huberfa622942017-03-24 17:25:37 +0100179 */
180 union {
181 uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */
182
183 /* only used for bit-field check */
184 struct {
185 uint32_t base :13,
186 :3,
187 limit :13,
188 :3;
189 } old_reg[MAX_NUM_FLREGS];
190 };
191};
192
David Hendricks8e762302017-08-09 22:21:31 -0700193#define MAX_NUM_MASTERS 6 /* 5 prior to C620/Lewisburg PCH */
Stefan Tauner1e146392011-09-15 23:52:55 +0000194struct ich_desc_master {
195 union {
Nico Huberfa622942017-03-24 17:25:37 +0100196 uint32_t FLMSTRs[MAX_NUM_MASTERS]; /* Flash Masters */
197 /* For pre-Skylake platforms */
Stefan Tauner1e146392011-09-15 23:52:55 +0000198 struct {
199 uint32_t BIOS_req_ID :16,
200 BIOS_descr_r :1,
201 BIOS_BIOS_r :1,
202 BIOS_ME_r :1,
203 BIOS_GbE_r :1,
204 BIOS_plat_r :1,
205 :3,
206 BIOS_descr_w :1,
207 BIOS_BIOS_w :1,
208 BIOS_ME_w :1,
209 BIOS_GbE_w :1,
210 BIOS_plat_w :1,
211 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000212 uint32_t ME_req_ID :16,
213 ME_descr_r :1,
214 ME_BIOS_r :1,
215 ME_ME_r :1,
216 ME_GbE_r :1,
217 ME_plat_r :1,
218 :3,
219 ME_descr_w :1,
220 ME_BIOS_w :1,
221 ME_ME_w :1,
222 ME_GbE_w :1,
223 ME_plat_w :1,
224 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000225 uint32_t GbE_req_ID :16,
226 GbE_descr_r :1,
227 GbE_BIOS_r :1,
228 GbE_ME_r :1,
229 GbE_GbE_r :1,
230 GbE_plat_r :1,
231 :3,
232 GbE_descr_w :1,
233 GbE_BIOS_w :1,
234 GbE_ME_w :1,
235 GbE_GbE_w :1,
236 GbE_plat_w :1,
237 :3;
238 };
Nico Huberfa622942017-03-24 17:25:37 +0100239 /* From Skylake on */
240 struct {
241 uint32_t :8,
242 read :12,
243 write :12;
244 } mstr[MAX_NUM_MASTERS];
Stefan Tauner1e146392011-09-15 23:52:55 +0000245 };
246};
247
Stefan Taunerb3850962011-12-24 00:00:32 +0000248struct ich_desc_north_strap {
249 union {
250 uint32_t STRPs[1]; /* current maximum: ich8 */
251 struct { /* ich8 */
252 struct { /* STRP2 (in the datasheet) */
253 uint32_t MDB :1,
254 :31;
255 };
256 } ich8;
257 };
258};
259
260struct ich_desc_south_strap {
261 union {
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000262 uint32_t STRPs[18]; /* current maximum: cougar point */
Stefan Taunerb3850962011-12-24 00:00:32 +0000263 struct { /* ich8 */
264 struct { /* STRP1 */
265 uint32_t ME_DISABLE :1,
266 :6,
267 TCOMODE :1,
268 ASD :7,
269 BMCMODE :1,
270 :3,
271 GLAN_PCIE_SEL :1,
272 GPIO12_SEL :2,
273 SPICS1_LANPHYPC_SEL :1,
274 MESM2SEL :1,
275 :1,
276 ASD2 :7;
277 };
278 } ich8;
279 struct { /* ibex peak */
280 struct { /* STRP0 */
281 uint32_t :1,
282 cs_ss2 :1,
283 :5,
284 SMB_EN :1,
285 SML0_EN :1,
286 SML1_EN :1,
287 SML1FRQ :2,
288 SMB0FRQ :2,
289 SML0FRQ :2,
290 :4,
291 LANPHYPC_GP12_SEL :1,
292 cs_ss1 :1,
293 :2,
294 DMI_REQID_DIS :1,
295 :4,
296 BBBS :2,
297 :1;
298 };
299 struct { /* STRP1 */
300 uint32_t cs_ss3 :4,
301 :28;
302 };
303 struct { /* STRP2 */
304 uint32_t :8,
305 MESMASDEN :1,
306 MESMASDA :7,
307 :8,
308 MESMI2CEN :1,
309 MESMI2CA :7;
310 };
311 struct { /* STRP3 */
312 uint32_t :32;
313 };
314 struct { /* STRP4 */
315 uint32_t PHYCON :2,
316 :6,
317 GBEMAC_SMBUS_ADDR_EN :1,
318 GBEMAC_SMBUS_ADDR :7,
319 :1,
320 GBEPHY_SMBUS_ADDR :7,
321 :8;
322 };
323 struct { /* STRP5 */
324 uint32_t :32;
325 };
326 struct { /* STRP6 */
327 uint32_t :32;
328 };
329 struct { /* STRP7 */
330 uint32_t MESMA2UDID_VENDOR :16,
331 MESMA2UDID_DEVICE :16;
332 };
333 struct { /* STRP8 */
334 uint32_t :32;
335 };
336 struct { /* STRP9 */
337 uint32_t PCIEPCS1 :2,
338 PCIEPCS2 :2,
339 PCIELR1 :1,
340 PCIELR2 :1,
341 DMILR :1,
342 :1,
343 PHY_PCIEPORTSEL :3,
344 PHY_PCIE_EN :1,
345 :20;
346 };
347 struct { /* STRP10 */
348 uint32_t :1,
349 ME_BOOT_FLASH :1,
350 cs_ss5 :1,
351 VE_EN :1,
352 :4,
353 MMDDE :1,
354 MMADDR :7,
355 cs_ss7 :1,
356 :1,
357 ICC_SEL :3,
358 MER_CL1 :1,
359 :10;
360 };
361 struct { /* STRP11 */
362 uint32_t SML1GPAEN :1,
363 SML1GPA :7,
364 :16,
365 SML1I2CAEN :1,
366 SML1I2CA :7;
367 };
368 struct { /* STRP12 */
369 uint32_t :32;
370 };
371 struct { /* STRP13 */
372 uint32_t :32;
373 };
374 struct { /* STRP14 */
375 uint32_t :8,
376 VE_EN2 :1,
377 :5,
378 VE_BOOT_FLASH :1,
379 :1,
380 BW_SSD :1,
381 NVMHCI_EN :1,
382 :14;
383 };
384 struct { /* STRP15 */
385 uint32_t :3,
386 cs_ss6 :2,
387 :1,
388 IWL_EN :1,
389 :1,
390 t209min :2,
391 :22;
392 };
393 } ibex;
394 struct { /* cougar point */
395 struct { /* STRP0 */
396 uint32_t :1,
397 cs_ss1 :1,
398 :5,
399 SMB_EN :1,
400 SML0_EN :1,
401 SML1_EN :1,
402 SML1FRQ :2,
403 SMB0FRQ :2,
404 SML0FRQ :2,
405 :4,
406 LANPHYPC_GP12_SEL :1,
407 LINKSEC_DIS :1,
408 :2,
409 DMI_REQID_DIS :1,
410 :4,
411 BBBS :2,
412 :1;
413 };
414 struct { /* STRP1 */
415 uint32_t cs_ss3 :4,
416 :4,
417 cs_ss2 :1,
418 :28;
419 };
420 struct { /* STRP2 */
421 uint32_t :8,
422 MESMASDEN :1,
423 MESMASDA :7,
424 MESMMCTPAEN :1,
425 MESMMCTPA :7,
426 MESMI2CEN :1,
427 MESMI2CA :7;
428 };
429 struct { /* STRP3 */
430 uint32_t :32;
431 };
432 struct { /* STRP4 */
433 uint32_t PHYCON :2,
434 :6,
435 GBEMAC_SMBUS_ADDR_EN :1,
436 GBEMAC_SMBUS_ADDR :7,
437 :1,
438 GBEPHY_SMBUS_ADDR :7,
439 :8;
440 };
441 struct { /* STRP5 */
442 uint32_t :32;
443 };
444 struct { /* STRP6 */
445 uint32_t :32;
446 };
447 struct { /* STRP7 */
448 uint32_t MESMA2UDID_VENDOR :16,
449 MESMA2UDID_DEVICE :16;
450 };
451 struct { /* STRP8 */
452 uint32_t :32;
453 };
454 struct { /* STRP9 */
455 uint32_t PCIEPCS1 :2,
456 PCIEPCS2 :2,
457 PCIELR1 :1,
458 PCIELR2 :1,
459 DMILR :1,
460 cs_ss4 :1,
461 PHY_PCIEPORTSEL :3,
462 PHY_PCIE_EN :1,
463 :2,
464 SUB_DECODE_EN :1,
465 :7,
466 PCHHOT_SML1ALERT_SEL :1,
467 :9;
468 };
469 struct { /* STRP10 */
470 uint32_t :1,
471 ME_BOOT_FLASH :1,
472 :6,
473 MDSMBE_EN :1,
474 MDSMBE_ADD :7,
475 :2,
476 ICC_SEL :3,
477 MER_CL1 :1,
478 ICC_PRO_SEL :1,
479 Deep_SX_EN :1,
480 ME_DBG_LAN :1,
481 :7;
482 };
483 struct { /* STRP11 */
484 uint32_t SML1GPAEN :1,
485 SML1GPA :7,
486 :16,
487 SML1I2CAEN :1,
488 SML1I2CA :7;
489 };
490 struct { /* STRP12 */
491 uint32_t :32;
492 };
493 struct { /* STRP13 */
494 uint32_t :32;
495 };
496 struct { /* STRP14 */
497 uint32_t :32;
498 };
499 struct { /* STRP15 */
500 uint32_t cs_ss6 :6,
501 IWL_EN :1,
502 cs_ss5 :2,
503 :4,
504 SMLINK1_THERM_SEL :1,
505 SLP_LAN_GP29_SEL :1,
506 :16;
507 };
508 struct { /* STRP16 */
509 uint32_t :32;
510 };
511 struct { /* STRP17 */
512 uint32_t ICML :1,
513 cs_ss7 :1,
514 :30;
515 };
516 } cougar;
517 };
518};
519
520struct ich_desc_upper_map {
521 union {
522 uint32_t FLUMAP1; /* Flash Upper Map 1 */
523 struct {
524 uint32_t VTBA :8, /* ME VSCC Table Base Address */
525 VTL :8, /* ME VSCC Table Length */
526 :16;
527 };
528 };
529 struct {
530 union { /* JEDEC-ID Register */
531 uint32_t JID;
532 struct {
533 uint32_t vid :8, /* Vendor ID */
534 cid0 :8, /* Component ID 0 */
535 cid1 :8, /* Component ID 1 */
536 :8;
537 };
538 };
539 union { /* Vendor Specific Component Capabilities */
540 uint32_t VSCC;
541 struct {
542 uint32_t ubes :2, /* Upper Block/Sector Erase Size */
543 uwg :1, /* Upper Write Granularity */
544 uwsr :1, /* Upper Write Status Required */
545 uwews :1, /* Upper Write Enable on Write Status */
546 :3,
547 ueo :8, /* Upper Erase Opcode */
548 lbes :2, /* Lower Block/Sector Erase Size */
549 lwg :1, /* Lower Write Granularity */
550 lwsr :1, /* Lower Write Status Required */
551 lwews :1, /* Lower Write Enable on Write Status */
552 :3,
553 leo :16; /* Lower Erase Opcode */
554 };
555 };
556 } vscc_table[128];
557};
Stefan Taunerb3850962011-12-24 00:00:32 +0000558
Stefan Tauner1e146392011-09-15 23:52:55 +0000559struct ich_descriptors {
560 struct ich_desc_content content;
561 struct ich_desc_component component;
562 struct ich_desc_region region;
563 struct ich_desc_master master;
Stefan Taunerb3850962011-12-24 00:00:32 +0000564 struct ich_desc_north_strap north;
565 struct ich_desc_south_strap south;
566 struct ich_desc_upper_map upper;
Stefan Tauner1e146392011-09-15 23:52:55 +0000567};
568
David Hendricks0eb00d42017-09-01 20:02:36 -0700569struct ich_layout {
570 struct flashrom_layout base;
David Hendricks7a8305f2017-09-01 20:16:58 -0700571 struct romentry entries[MAX_NUM_FLREGS];
David Hendricks0eb00d42017-09-01 20:02:36 -0700572};
573
Nico Huberfa622942017-03-24 17:25:37 +0100574ssize_t ich_number_of_regions(enum ich_chipset cs, const struct ich_desc_content *content);
575ssize_t ich_number_of_masters(enum ich_chipset cs, const struct ich_desc_content *content);
576
Nico Huber67d71792017-06-17 03:10:15 +0200577void prettyprint_ich_chipset(enum ich_chipset cs);
Stefan Taunerb3850962011-12-24 00:00:32 +0000578void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000579
Nico Huberfa622942017-03-24 17:25:37 +0100580void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *content);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000581void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100582void prettyprint_ich_descriptor_region(enum ich_chipset cs, const struct ich_descriptors *desc);
583void prettyprint_ich_descriptor_master(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000584
Stefan Taunerb3850962011-12-24 00:00:32 +0000585void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
586void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100587int read_ich_descriptors_from_dump(const uint32_t *dump, size_t len, enum ich_chipset *cs, struct ich_descriptors *desc);
Stefan Taunerb3850962011-12-24 00:00:32 +0000588
Nico Huberd54e4f42017-03-23 23:45:47 +0100589int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000590int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx);
Stefan Tauner1e146392011-09-15 23:52:55 +0000591
Nico Huber305f4172013-06-14 11:55:26 +0200592int layout_from_ich_descriptors(struct ich_layout *, const void *dump, size_t len);
593
Stefan Tauner1e146392011-09-15 23:52:55 +0000594#endif /* __ICH_DESCRIPTORS_H__ */