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Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Datasheet:
23 * - Name: Intel 82802AB/82802AC Firmware Hub (FWH)
24 * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm
25 * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf
26 * - Order number: 290658-004
27 */
28
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000029#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "chipdrivers.h"
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000031
Sean Nelson28accc22010-03-19 18:47:06 +000032void print_status_82802ab(uint8_t status)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000033{
Sean Nelsoned479d22010-03-24 23:14:32 +000034 msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
35 msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
36 msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
37 msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
38 msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
39 msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
40 msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000041}
42
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000043int probe_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000044{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000045 chipaddr bios = flash->virtual_memory;
Uwe Hermann91f4afa2011-07-28 08:13:25 +000046 uint8_t id1, id2, flashcontent1, flashcontent2;
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000047 int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000048
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000049 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000050 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000051 programmer_delay(10);
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000052
53 /* Enter ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000054 chip_writeb(flash, 0x90, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000055 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000056
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000057 id1 = chip_readb(flash, bios + (0x00 << shifted));
58 id2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000059
60 /* Leave ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000061 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000062
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000063 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000064
Sean Nelsoned479d22010-03-24 23:14:32 +000065 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000066
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000067 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +000068 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000069
Uwe Hermann91f4afa2011-07-28 08:13:25 +000070 /*
71 * Read the product ID location again. We should now see normal
72 * flash contents.
73 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000074 flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
75 flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000076
77 if (id1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +000078 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000079 if (id2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +000080 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000081
Sean Nelsoned479d22010-03-24 23:14:32 +000082 msg_cdbg("\n");
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000083 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000084 return 0;
85
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000086 if (flash->chip->feature_bits & FEATURE_REGISTERMAP)
Carl-Daniel Hailfinger81449a22010-03-15 03:48:42 +000087 map_flash_registers(flash);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000088
89 return 1;
90}
91
Stefan Tauner4404f732013-09-12 08:28:56 +000092/* FIXME: needs timeout */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000093uint8_t wait_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000094{
95 uint8_t status;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000096 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000097
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000098 chip_writeb(flash, 0x70, bios);
99 if ((chip_readb(flash, bios) & 0x80) == 0) { // it's busy
100 while ((chip_readb(flash, bios) & 0x80) == 0) ;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000101 }
102
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000103 status = chip_readb(flash, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000104
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +0000105 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000106 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000107
108 return status;
109}
110
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000111int unlock_82802ab(struct flashctx *flash)
Sean Nelson28accc22010-03-19 18:47:06 +0000112{
113 int i;
114 //chipaddr wrprotect = flash->virtual_registers + page + 2;
115
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000116 for (i = 0; i < flash->chip->total_size * 1024; i+= flash->chip->page_size)
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000117 chip_writeb(flash, 0, flash->virtual_registers + i + 2);
Sean Nelson28accc22010-03-19 18:47:06 +0000118
119 return 0;
120}
121
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000122int erase_block_82802ab(struct flashctx *flash, unsigned int page,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000123 unsigned int pagesize)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000124{
Sean Nelson54596372010-01-09 05:30:14 +0000125 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000126 uint8_t status;
127
128 // clear status register
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000129 chip_writeb(flash, 0x50, bios + page);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000130
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000131 // now start it
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000132 chip_writeb(flash, 0x20, bios + page);
133 chip_writeb(flash, 0xd0, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000134 programmer_delay(10);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000135
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000136 // now let's see what the register is
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000137 status = wait_82802ab(flash);
Sean Nelson28accc22010-03-19 18:47:06 +0000138 print_status_82802ab(status);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000139
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000140 /* FIXME: Check the status register for errors. */
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000141 return 0;
142}
143
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000144/* chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000145int write_82802ab(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000146{
147 int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000148 chipaddr dst = flash->virtual_memory + start;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000149
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000150 for (i = 0; i < len; i++) {
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000151 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000152 chip_writeb(flash, 0x40, dst);
153 chip_writeb(flash, *src++, dst++);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000154 wait_82802ab(flash);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000155 }
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000156
157 /* FIXME: Ignore errors for now. */
158 return 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000159}
160
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000161int unlock_28f004s5(struct flashctx *flash)
Sean Nelsondee4a832010-03-22 04:39:31 +0000162{
163 chipaddr bios = flash->virtual_memory;
Sean Nelson4e54de92010-03-22 07:03:26 +0000164 uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0;
165 int i;
Sean Nelsondee4a832010-03-22 04:39:31 +0000166
167 /* Clear status register */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000168 chip_writeb(flash, 0x50, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000169
170 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000171 chip_writeb(flash, 0x90, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000172
173 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000174 mcfg = chip_readb(flash, bios + 0x3);
Sean Nelsoned479d22010-03-24 23:14:32 +0000175 msg_cdbg("master lock is ");
Sean Nelsondee4a832010-03-22 04:39:31 +0000176 if (mcfg) {
177 msg_cdbg("locked!\n");
178 } else {
179 msg_cdbg("unlocked!\n");
180 can_unlock = 1;
181 }
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000182
Sean Nelsondee4a832010-03-22 04:39:31 +0000183 /* Read block lock-bits */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000184 for (i = 0; i < flash->chip->total_size * 1024; i+= (64 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000185 bcfg = chip_readb(flash, bios + i + 2); // read block lock config
Sean Nelsondee4a832010-03-22 04:39:31 +0000186 msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un");
187 if (bcfg) {
188 need_unlock = 1;
189 }
190 }
191
192 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000193 chip_writeb(flash, 0xFF, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000194
195 /* Unlock: clear block lock-bits, if needed */
196 if (can_unlock && need_unlock) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000197 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000198 chip_writeb(flash, 0x60, bios);
199 chip_writeb(flash, 0xD0, bios);
200 chip_writeb(flash, 0xFF, bios);
Sean Nelsoned479d22010-03-24 23:14:32 +0000201 msg_cdbg("Done!\n");
Sean Nelsondee4a832010-03-22 04:39:31 +0000202 }
203
204 /* Error: master locked or a block is locked */
205 if (!can_unlock && need_unlock) {
206 msg_cerr("At least one block is locked and lockdown is active!\n");
207 return -1;
208 }
209
210 return 0;
211}
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000212
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000213int unlock_lh28f008bjt(struct flashctx *flash)
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000214{
215 chipaddr bios = flash->virtual_memory;
216 uint8_t mcfg, bcfg;
217 uint8_t need_unlock = 0, can_unlock = 0;
218 int i;
219
220 /* Wait if chip is busy */
221 wait_82802ab(flash);
222
223 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000224 chip_writeb(flash, 0x90, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000225
226 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000227 mcfg = chip_readb(flash, bios + 0x3);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000228 msg_cdbg("master lock is ");
229 if (mcfg) {
230 msg_cdbg("locked!\n");
231 } else {
232 msg_cdbg("unlocked!\n");
233 can_unlock = 1;
234 }
235
236 /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000237 for (i = 0; i < flash->chip->total_size * 1024;
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000238 i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000239 bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000240 msg_cdbg("block lock at %06x is %slocked!\n", i,
241 bcfg ? "" : "un");
242 if (bcfg)
243 need_unlock = 1;
244 }
245
246 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000247 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000248
249 /* Unlock: clear block lock-bits, if needed */
250 if (can_unlock && need_unlock) {
251 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000252 chip_writeb(flash, 0x60, bios);
253 chip_writeb(flash, 0xD0, bios);
254 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000255 wait_82802ab(flash);
256 msg_cdbg("Done!\n");
257 }
258
259 /* Error: master locked or a block is locked */
260 if (!can_unlock && need_unlock) {
261 msg_cerr("At least one block is locked and lockdown is active!\n");
262 return -1;
263 }
264
265 return 0;
266}