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Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __FLASHCHIPS_H__
25#define __FLASHCHIPS_H__ 1
26
27/*
28 * Please keep this list sorted alphabetically by manufacturer. The first
29 * entry of each section should be the manufacturer ID, followed by the
30 * list of devices from that manufacturer (sorted by device IDs).
31 *
32 * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
33 * continuation code.
34 * SPI parts have 16-bit device IDs if they support RDID.
35 */
36
37#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
38
39#define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
40
41#define AMD_ID 0x01 /* AMD */
Uwe Hermanna8b37272009-06-19 15:54:39 +000042#define AM_29F010B 0x20 /* Same as Am29F010A */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000043#define AM_29F002BT 0xB0
44#define AM_29F002BB 0x34
45#define AM_29F040B 0xA4
46#define AM_29F080B 0xD5
47#define AM_29LV040B 0x4F
48#define AM_29LV081B 0x38
49#define AM_29F016D 0xAD
50
51#define AMIC_ID 0x7F37 /* AMIC */
52#define AMIC_ID_NOPREFIX 0x37 /* AMIC */
53#define AMIC_A25L40P 0x2013
54#define AMIC_A29002B 0x0d
55#define AMIC_A29002T 0x8c
56#define AMIC_A29040B 0x86
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +000057#define AMIC_A29400T 0xB0 /* Same as 294001T */
58#define AMIC_A29400U 0x31 /* Same as A294001U */
59#define AMIC_A29800T 0x0E
60#define AMIC_A29800U 0x8F
61#define AMIC_A29L004T 0x34 /* Same as A29L400T */
62#define AMIC_A29L004U 0xB5 /* Same as A29L400U */
63#define AMIC_A29L008T 0x1A /* Same as A29L800T */
64#define AMIC_A29L008U 0x9B /* Same as A29L800U */
65#define AMIC_A29L040 0x92
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000066#define AMIC_A49LF040A 0x9d
67
68/* This chip vendor/device ID is probably a misinterpreted LHA header. */
69#define ASD_ID 0x25 /* ASD, not listed in JEP106W */
70#define ASD_AE49F2008 0x52
71
72#define ATMEL_ID 0x1F /* Atmel */
73#define AT_25DF021 0x4300
74#define AT_25DF041A 0x4401
75#define AT_25DF081 0x4502
76#define AT_25DF161 0x4602
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +000077#define AT_25DF321 0x4700 /* Same as 26DF321 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000078#define AT_25DF321A 0x4701
79#define AT_25DF641 0x4800
80#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */
81#define AT_25F512B 0x6500
82#define AT_25FS010 0x6601
83#define AT_25FS040 0x6604
84#define AT_26DF041 0x4400
85#define AT_26DF081 0x4500 /* guessed, no datasheet available */
86#define AT_26DF081A 0x4501
87#define AT_26DF161 0x4600
88#define AT_26DF161A 0x4601
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +000089#define AT_26DF321 0x4700 /* Same as 25DF321 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000090#define AT_26F004 0x0400
91#define AT_29C040A 0xA4
92#define AT_29C010A 0xD5
93#define AT_29C020 0xDA
94#define AT_29C512 0x5D
95#define AT_45BR3214B /* No ID available */
96#define AT_45CS1282 0x2920
97#define AT_45D011 /* No ID available */
98#define AT_45D021A /* No ID available */
99#define AT_45D041A /* No ID available */
100#define AT_45D081A /* No ID available */
101#define AT_45D161 /* No ID available */
102#define AT_45DB011 /* No ID available */
103#define AT_45DB011B /* No ID available */
104#define AT_45DB011D 0x2200
105#define AT_45DB021A /* No ID available */
106#define AT_45DB021B /* No ID available */
107#define AT_45DB021D 0x2300
108#define AT_45DB041A /* No ID available */
109#define AT_45DB041D 0x2400
110#define AT_45DB081A /* No ID available */
111#define AT_45DB081D 0x2500
112#define AT_45DB161 /* No ID available */
113#define AT_45DB161B /* No ID available */
114#define AT_45DB161D 0x2600
115#define AT_45DB321 /* No ID available */
116#define AT_45DB321B /* No ID available */
117#define AT_45DB321C 0x2700
118#define AT_45DB321D 0x2701 /* Buggy data sheet */
119#define AT_45DB642 /* No ID available */
120#define AT_45DB642D 0x2800
121#define AT_49BV512 0x03
122#define AT_49F002N 0x07 /* for AT49F002(N) */
123#define AT_49F002NT 0x08 /* for AT49F002(N)T */
124
125#define CATALYST_ID 0x31 /* Catalyst */
126
127#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
128#define EMST_F49B002UA 0x00
129
130/*
131 * EN25 chips are SPI, first byte of device ID is memory type,
132 * second byte of device ID is log(bitsize)-9.
133 * Vendor and device ID of EN29 series are both prefixed with 0x7F, which
134 * is the continuation code for IDs in bank 2.
135 * Vendor ID of EN25 series is NOT prefixed with 0x7F, this results in
136 * a collision with Mitsubishi. Mitsubishi once manufactured flash chips.
137 * Let's hope they are not manufacturing SPI flash chips as well.
138 */
139#define EON_ID 0x7F1C /* EON Silicon Devices */
140#define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000141#define EN_25B05 0x2010 /* Same as P05, 2^19 kbit or 2^16 kByte */
142#define EN_25B10 0x2011 /* Same as P10 */
143#define EN_25B20 0x2012 /* Same as P20 */
144#define EN_25B40 0x2013 /* Same as P40 */
145#define EN_25B80 0x2014 /* Same as P80 */
146#define EN_25B16 0x2015 /* Same as P16 */
147#define EN_25B32 0x2016 /* Same as P32 */
148#define EN_25B64 0x2017 /* Same as P64 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000149#define EN_25D16 0x3015
150#define EN_25F05 0x3110
151#define EN_25F10 0x3111
152#define EN_25F20 0x3112
153#define EN_25F40 0x3113
154#define EN_25F80 0x3114
155#define EN_25F16 0x3115
156#define EN_25F32 0x3116
157#define EN_29F512 0x7F21
158#define EN_29F010 0x7F20
159#define EN_29F040A 0x7F04
160#define EN_29LV010 0x7F6E
161#define EN_29LV040A 0x7F4F /* EN_29LV040(A) */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000162#define EN_29F002T 0x7F92 /* Same as EN29F002A */
163#define EN_29F002B 0x7F97 /* Same as EN29F002AN */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000164
165#define FUJITSU_ID 0x04 /* Fujitsu */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000166#define MBM29DL400BC 0x0F
167#define MBM29DL400TC 0x0C
168#define MBM29DL800BA 0xCB
169#define MBM29DL800TA 0x4A
170#define MBM29F002BC 0x34
171#define MBM29F002TC 0xB0
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000172#define MBM29F004BC 0x7B
173#define MBM29F004TC 0x77
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000174#define MBM29F040C 0xA4
175#define MBM29F080A 0xD5
176#define MBM29F200BC 0x57
177#define MBM29F200TC 0x51
178#define MBM29F400BC 0xAB
179#define MBM29F400TC 0x23
180#define MBM29F800BA 0x58
181#define MBM29F800TA 0xD6
182#define MBM29LV002BC 0xC2
183#define MBM29LV002TC 0x40
184#define MBM29LV004BC 0xB6
185#define MBM29LV004TC 0xB5
186#define MBM29LV008BA 0x37
187#define MBM29LV008TA 0x3E
188#define MBM29LV080A 0x38
189#define MBM29LV200BC 0xBF
190#define MBM29LV200TC 0x3B
191#define MBM29LV400BC 0xBA
192#define MBM29LV400TC 0xB9
193#define MBM29LV800BA 0x5B /* Same as MBM29LV800BE */
194#define MBM29LV800TA 0xDA /* Same as MBM29LV800TE */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000195
196#define HYUNDAI_ID 0xAD /* Hyundai */
197
198#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
199#define IM_29F004B 0xAE
200#define IM_29F004T 0xAF
201
202#define INTEL_ID 0x89 /* Intel */
203#define I_82802AB 0xAD
204#define I_82802AC 0xAC
205#define P28F001BXT 0x94 /* 28F001BX-T */
206#define P28F001BXB 0x95 /* 28F001BX-B */
207
208#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */
209
210/*
211 * MX25 chips are SPI, first byte of device ID is memory type,
212 * second byte of device ID is log(bitsize)-9.
213 * Generalplus SPI chips seem to be compatible with Macronix
214 * and use the same set of IDs.
215 */
216#define MX_ID 0xC2 /* Macronix (MX) */
217#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
218#define MX_25L1005 0x2011
219#define MX_25L2005 0x2012
220#define MX_25L4005 0x2013 /* MX25L4005{,A} */
221#define MX_25L8005 0x2014
222#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */
223#define MX_25L3205 0x2016 /* MX25L3205{,A} */
224#define MX_25L6405 0x2017 /* MX25L3205{,D} */
225#define MX_25L12805 0x2018 /* MX25L12805 */
226#define MX_25L1635D 0x2415
227#define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000228#define MX_29F002B 0x34 /* Same as MX29F002NB */
229#define MX_29F002T 0xB0 /* Same as MX29F002NT */
230#define MX_29F004B 0x46
231#define MX_29F004T 0x45
232#define MX_29F022T 0x36 /* Same as MX29F022NT */
233#define MX_29F040 0xA4 /* Same as MX29F040C */
234#define MX_29F080 0xD5
235#define MX_29F200B 0x57 /* Same as MX29F200CB */
236#define MX_29F200T 0x51 /* Same as MX29F200CT */
237#define MX_29F400B 0xAB /* Same as MX29F400CB */
238#define MX_29F400T 0x23 /* Same as MX29F400CT */
239#define MX_29F800B 0x58
240#define MX_29F800T 0xD6
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000241#define MX_29LV002CB 0x5A
242#define MX_29LV002CT 0x59
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000243#define MX_29LV004B 0xB6 /* Same as MX29LV004CB */
244#define MX_29LV004T 0xB5 /* Same as MX29LV004CT */
245#define MX_29LV008B 0x37 /* Same as MX29LV008CB */
246#define MX_29LV008T 0x3E /* Same as MX29LV008CT */
247#define MX_29LV040 0x4F /* Same as MX29LV040C */
248#define MX_29LV081 0x38
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000249#define MX_29LV128DB 0x7A
250#define MX_29LV128DT 0x7E
251#define MX_29LV160DB 0x49 /* Same as MX29LV161DB/MX29LV160CB */
252#define MX_29LV160DT 0xC4 /* Same as MX29LV161DT/MX29LV160CT */
253#define MX_29LV320DB 0xA8 /* Same as MX29LV321DB */
254#define MX_29LV320DT 0xA7 /* Same as MX29LV321DT */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000255#define MX_29LV400B 0xBA /* Same as MX29LV400CB */
256#define MX_29LV400T 0xB9 /* Same as MX29LV400CT */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000257#define MX_29LV640DB 0xCB /* Same as MX29LV640EB */
258#define MX_29LV640DT 0xC9 /* Same as MX29LV640ET */
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000259#define MX_29LV800B 0x5B /* Same as MX29LV800CB */
260#define MX_29LV800T 0xDA /* Same as MX29LV800CT */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000261#define MX_29SL402CB 0xF1
262#define MX_29SL402CT 0x70
263#define MX_29SL800CB 0x6B /* Same as MX29SL802CB */
264#define MX_29SL800CT 0xEA /* Same as MX29SL802CT */
265
266/*
267 * Programmable Micro Corp is listed in JEP106W in bank 2, so it should
268 * have a 0x7F continuation code prefix.
269 */
270#define PMC_ID 0x7F9D /* PMC */
271#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
272#define PMC_25LV512 0x7B
273#define PMC_25LV010 0x7C
274#define PMC_25LV020 0x7D
275#define PMC_25LV040 0x7E
276#define PMC_25LV080B 0x13
277#define PMC_25LV016B 0x14
278#define PMC_29F002T 0x1D
279#define PMC_29F002B 0x2D
280#define PMC_39LV512 0x1B
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000281#define PMC_39F010 0x1C /* Same as Pm39LV010 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000282#define PMC_39LV020 0x3D
283#define PMC_39LV040 0x3E
284#define PMC_39F020 0x4D
285#define PMC_39F040 0x4E
286#define PMC_49FL002 0x6D
287#define PMC_49FL004 0x6E
288
289#define SHARP_ID 0xB0 /* Sharp */
290#define SHARP_LHF00L04 0xCF
291
292/*
293 * Spansion was previously a joint venture of AMD and Fujitsu.
294 * S25 chips are SPI. The first device ID byte is memory type and
295 * the second device ID byte is memory capacity.
296 */
297#define SPANSION_ID 0x01 /* Spansion */
298#define SPANSION_S25FL016A 0x0214
299
300/*
301 * SST25 chips are SPI, first byte of device ID is memory type, second
302 * byte of device ID is related to log(bitsize) at least for some chips.
303 */
304#define SST_ID 0xBF /* SST */
305#define SST_25WF512 0x2501
306#define SST_25WF010 0x2502
307#define SST_25WF020 0x2503
308#define SST_25WF040 0x2504
309#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */
310#define SST_25VF010_REMS 0x49 /* REMS or RES opcode */
311#define SST_25VF020_REMS 0x43 /* REMS or RES opcode */
312#define SST_25VF040_REMS 0x44 /* REMS or RES opcode */
313#define SST_25VF040B 0x258D
314#define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */
315#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */
316#define SST_25VF080B 0x258E
317#define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */
318#define SST_25VF016B 0x2541
319#define SST_25VF032B 0x254A
320#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */
321#define SST_26VF016 0x2601
322#define SST_26VF032 0x2602
323#define SST_27SF512 0xA4
324#define SST_27SF010 0xA5
325#define SST_27SF020 0xA6
326#define SST_27VF010 0xA9
327#define SST_27VF020 0xAA
328#define SST_28SF040 0x04
329#define SST_29EE512 0x5D
330#define SST_29EE010 0x07
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000331#define SST_29LE010 0x08 /* Same as SST29VE010 */
332#define SST_29EE020A 0x10 /* Same as SST29EE020 */
333#define SST_29LE020 0x12 /* Same as SST29VE020 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000334#define SST_29SF020 0x24
335#define SST_29VF020 0x25
336#define SST_29SF040 0x13
337#define SST_29VF040 0x14
338#define SST_39SF010 0xB5
339#define SST_39SF020 0xB6
340#define SST_39SF040 0xB7
341#define SST_39VF512 0xD4
342#define SST_39VF010 0xD5
343#define SST_39VF020 0xD6
344#define SST_39VF040 0xD7
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000345#define SST_39VF080 0xD8 /* Same as SST_39LF080/39VF080/39VF088 */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000346#define SST_49LF040B 0x50
347#define SST_49LF040 0x51
348#define SST_49LF020 0x61
349#define SST_49LF020A 0x52
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000350#define SST_49LF030A 0x1C
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000351#define SST_49LF080A 0x5B
352#define SST_49LF002A 0x57
353#define SST_49LF003A 0x1B
354#define SST_49LF004A 0x60
355#define SST_49LF008A 0x5A
356#define SST_49LF004C 0x54
357#define SST_49LF008C 0x59
358#define SST_49LF016C 0x5C
359#define SST_49LF160C 0x4C
360
361/*
362 * ST25P chips are SPI, first byte of device ID is memory type, second
363 * byte of device ID is related to log(bitsize) at least for some chips.
364 */
365#define ST_ID 0x20 /* ST / SGS/Thomson */
366#define ST_M25P05A 0x2010
Carl-Daniel Hailfinger32961be2009-07-23 01:40:20 +0000367#define ST_M25P05_RES 0x10 /* Same code as M25P10. */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000368#define ST_M25P10A 0x2011
Carl-Daniel Hailfinger32961be2009-07-23 01:40:20 +0000369#define ST_M25P10_RES 0x10 /* Same code as M25P05. */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000370#define ST_M25P20 0x2012
371#define ST_M25P40 0x2013
372#define ST_M25P40_RES 0x12
373#define ST_M25P80 0x2014
374#define ST_M25P16 0x2015
375#define ST_M25P32 0x2016
376#define ST_M25P64 0x2017
377#define ST_M25P128 0x2018
378#define ST_M25PE10 0x8011
379#define ST_M25PE20 0x8012
380#define ST_M25PE40 0x8013
381#define ST_M25PE80 0x8014
382#define ST_M25PE16 0x8015
383#define ST_M50FLW040A 0x08
384#define ST_M50FLW040B 0x28
385#define ST_M50FLW080A 0x80
386#define ST_M50FLW080B 0x81
387#define ST_M50FW002 0x29
388#define ST_M50FW040 0x2C
389#define ST_M50FW080 0x2D
390#define ST_M50FW016 0x2E
391#define ST_M50LPW116 0x30
392#define ST_M29F002B 0x34
393#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000394#define ST_M29F040B 0xE2
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000395#define ST_M29F080 0xF1
396#define ST_M29F200BT 0xD3
397#define ST_M29F200BB 0xD4
398#define ST_M29F400BT 0xD5
399#define ST_M29F400BB 0xD6
400#define ST_M29F800DB 0x58
401#define ST_M29F800DT 0xEC
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000402#define ST_M29W010B 0x23
403#define ST_M29W040B 0xE3
404
405#define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */
406#define S29C51001T 0x01
407#define S29C51002T 0x02
408#define S29C51004T 0x03
409#define S29C31004T 0x63
410
411#define TI_ID 0x97 /* Texas Instruments */
412#define TI_OLD_ID 0x01 /* TI chips from last century */
413#define TI_TMS29F002RT 0xB0
414#define TI_TMS29F002RB 0x34
415
416/*
417 * W25X chips are SPI, first byte of device ID is memory type, second
418 * byte of device ID is related to log(bitsize).
419 */
420#define WINBOND_ID 0xDA /* Winbond */
421#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */
422#define W_25X10 0x3011
423#define W_25X20 0x3012
424#define W_25X40 0x3013
425#define W_25X80 0x3014
426#define W_25X16 0x3015
427#define W_25X32 0x3016
428#define W_25X64 0x3017
429#define W_29C011 0xC1
430#define W_29C020C 0x45
431#define W_29C040P 0x46
432#define W_29EE011 0xC1
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000433#define W_39L020 0xB5
434#define W_39L040 0xB6
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000435#define W_39V040FA 0x34
436#define W_39V040A 0x3D
437#define W_39V040B 0x54
438#define W_39V040C 0x50
439#define W_39V080A 0xD0
440#define W_39V080FA 0xD3
441#define W_39V080FA_DM 0x93
442#define W_49F002U 0x0B
Carl-Daniel Hailfinger350a0c32009-07-24 13:59:27 +0000443#define W_49F020 0x8C
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +0000444#define W_49V002A 0xB0
445#define W_49V002FA 0x32
446
447#endif /* !FLASHCHIPS_H */