blob: 60498b11f6177407a637a61423da0cdc3becbd84 [file] [log] [blame]
Uwe Hermann2bc98f62009-09-30 18:29:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
Uwe Hermann2bc98f62009-09-30 18:29:55 +000023#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000024#include "programmer.h"
Uwe Hermann2bc98f62009-09-30 18:29:55 +000025
26#define PCI_VENDOR_ID_NVIDIA 0x10de
27
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +000028/* Mask to restrict flash accesses to a 128kB memory window.
29 * FIXME: Is this size a one-fits-all or card dependent?
30 */
31#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
32
Uwe Hermann2bc98f62009-09-30 18:29:55 +000033uint8_t *nvidia_bar;
34
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000035const struct pcidev_status gfx_nvidia[] = {
Michael Karcher84486392010-02-24 00:04:40 +000036 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
37 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
38 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
39 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
40 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
41 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
42 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
43 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
44 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
45 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
46 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
47 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
48 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
49 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
50 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
51 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
52 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
53 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
54 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
55 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
56 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
57 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
58 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
Uwe Hermann2bc98f62009-09-30 18:29:55 +000059
60 {},
61};
62
63int gfxnvidia_init(void)
64{
65 uint32_t reg32;
66
67 get_io_perms();
68
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000069 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000070
Uwe Hermann2bc98f62009-09-30 18:29:55 +000071 io_base_addr += 0x300000;
Sean Nelson8e5e73e2010-01-09 23:54:05 +000072 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
Uwe Hermann2bc98f62009-09-30 18:29:55 +000073
74 /* Allow access to flash interface (will disable screen). */
75 reg32 = pci_read_long(pcidev_dev, 0x50);
76 reg32 &= ~(1 << 0);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000077 rpci_write_long(pcidev_dev, 0x50, reg32);
Uwe Hermann2bc98f62009-09-30 18:29:55 +000078
79 nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024);
80
81 buses_supported = CHIP_BUSTYPE_PARALLEL;
82
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +000083 /* Write/erase doesn't work. */
84 programmer_may_write = 0;
85
Uwe Hermann2bc98f62009-09-30 18:29:55 +000086 return 0;
87}
88
89int gfxnvidia_shutdown(void)
90{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000091 /* Flash interface access is disabled (and screen enabled) automatically
92 * by PCI restore.
93 */
Uwe Hermann2bc98f62009-09-30 18:29:55 +000094 pci_cleanup(pacc);
95 release_io_perms();
96 return 0;
97}
98
99void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr)
100{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000101 pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000102}
103
104uint8_t gfxnvidia_chip_readb(const chipaddr addr)
105{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000106 return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000107}