)]}'
{
  "commit": "f5fcd742a0568aaf50274bc32e1206f99d65a8b8",
  "tree": "efdc370c3cc1fcca883364200bc0b6fff5db83ae",
  "parents": [
    "2d614d61c39eefb2796a6edaecb88a0b31650f3c"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Mar 11 17:11:12 2023 +0000"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Mar 14 23:31:10 2023 +0000"
  },
  "message": "amd_spi100: Revise 4BA support\n\nWith current SoCs, a flash bigger than 16MiB can\u0027t be fully\nmemory mapped. Also, the memory mapping doesn\u0027t necessarily\nshow us the expected window of the flash.\n\nSo, we consider a memory-mapped read only if we know that\nthe SPI controller\n* sends 32-bit addresses, and\n* doesn\u0027t remap any address bits.\n\nMoreover, we disable support for 4BA mode changes, as we\ncurrently don\u0027t reset the chip state and don\u0027t know if the\ncontroller feels in charge of these.\n\nSending native 4BA commands, however, shouldn\u0027t be a problem,\nso enable these.\n\nChange-Id: I899a89067774334fe15b05bf0b7f2baed5068353\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73677\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a09aea6061a659aa63a726aab4ff54e25c47d96a",
      "old_mode": 33188,
      "old_path": "amd_spi100.c",
      "new_id": "a6ad8c3e6ee4dc26f33e30241b63f8451e869129",
      "new_mode": 33188,
      "new_path": "amd_spi100.c"
    }
  ]
}