ichspi: Add Intel Arrow Lake support
ARL looks much like a desktop version of Meteor Lake. Hardware registers
seem to be the same, and the descriptor mostly differs in strap settings
(as far as we are concerned).
Odd enough, the old (pre 500 series) format for processor straps is used
again. For the descriptor detection, we shuffle the old default for Ibex
Peak around, and make Arrow Lake the default for everything with over 80
PCH traps.
Tested `ich_descriptors_tool' output for a GIGABYTE Z890M GAMING X BIOS.
Documents used:
* Intel® Core™ Ultra 200S Series Processors Datasheet, Volumes 1 and 2
* Arrow Lake-S and Arrow Lake-HX Client Platform
SPI Programming Guide
Change-Id: Ibaaeb896273eed3806561ba8c01d89770d27ff18
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/270
diff --git a/chipset_enable.c b/chipset_enable.c
index bb6b034..8818dcd 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -708,6 +708,7 @@
case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_ARROW_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1039,6 +1040,12 @@
return enable_flash_pch_spidev(spi_dev, name, CHIPSET_LUNAR_LAKE);
}
+static int enable_flash_arl(struct flashprog_programmer *const prog,
+ struct pci_dev *const spi_dev, const char *const name)
+{
+ return enable_flash_pch_spidev(spi_dev, name, CHIPSET_ARROW_LAKE);
+}
+
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@@ -2242,6 +2249,7 @@
{0x8086, 0x18e0, ANY_REV, B_S, NT, "Intel", "Snow Ridge", enable_flash_snowridge},
{0x8086, 0x7e23, ANY_REV, B_S, DEP, "Intel", "Meteor Lake", enable_flash_mtl},
{0x8086, 0xa823, ANY_REV, B_S, NT, "Intel", "Lunar Lake", enable_flash_lnl},
+ {0x8086, 0xae23, ANY_REV, B_S, NT, "Intel", "Arrow Lake", enable_flash_arl},
#endif
{0},
};