diff --git a/chipset_enable.c b/chipset_enable.c
index bb6b034..8818dcd 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -708,6 +708,7 @@
 	case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_LUNAR_LAKE:
+	case CHIPSET_ARROW_LAKE:
 		boot_straps = boot_straps_apl;
 		break;
 	case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1039,6 +1040,12 @@
 	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_LUNAR_LAKE);
 }
 
+static int enable_flash_arl(struct flashprog_programmer *const prog,
+			    struct pci_dev *const spi_dev, const char *const name)
+{
+	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_ARROW_LAKE);
+}
+
 /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
  * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
  *
@@ -2242,6 +2249,7 @@
 	{0x8086, 0x18e0,   ANY_REV, B_S,    NT,  "Intel", "Snow Ridge",			enable_flash_snowridge},
 	{0x8086, 0x7e23,   ANY_REV, B_S,    DEP, "Intel", "Meteor Lake",		enable_flash_mtl},
 	{0x8086, 0xa823,   ANY_REV, B_S,    NT,  "Intel", "Lunar Lake",			enable_flash_lnl},
+	{0x8086, 0xae23,   ANY_REV, B_S,    NT,  "Intel", "Arrow Lake",			enable_flash_arl},
 #endif
 	{0},
 };