)]}'
{
  "commit": "3750986348cb99b8f0d828b73972b545a2f9c878",
  "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315",
  "parents": [
    "908adf4589d34eaf3bd8395afa52aed8c8887cfd"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Fri Jan 18 14:23:02 2019 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Jul 06 17:15:58 2019 +0000"
  },
  "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "89458c6a7f362921e7c135422318fe4e9913a9d8",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "24ac64a335de1f4bcb8f03cc38f772d61d25a878",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    },
    {
      "type": "modify",
      "old_id": "e34289865e7573e7c3011497d57343d514d0cf4e",
      "old_mode": 33188,
      "old_path": "programmer.h",
      "new_id": "f4e8b4652b6cc28137b889821b304f4a93e84558",
      "new_mode": 33188,
      "new_path": "programmer.h"
    }
  ]
}