)]}'
{
  "log": [
    {
      "commit": "fdd93659e03396051940988de328f28cdb7d448c",
      "tree": "e20caca16f761188abb51d83efec2ec06ccb8afd",
      "parents": [
        "afadcace9e96289e3aff808c4fac5830c11bdc6c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Feb 08 13:41:38 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 03 15:24:14 2017 +0200"
      },
      "message": "gma broxton: Add signal level control for DDI PHYs\n\nOther than for the DDIs of the Core processor series, we don\u0027t select\nsignal levels from a preconfigured set but have to program the indivi-\ndual values.\n\nChange-Id: I3ab4d5e2ed47db0d4ce47a17c4a5fb08b5416bc2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18425\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "afadcace9e96289e3aff808c4fac5830c11bdc6c",
      "tree": "9cb10bccb194c7504a14c6f7e6f7fd7d97d3e0e6",
      "parents": [
        "4b0239f549c99b1c393f099fe21c7055860fbe7a"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Feb 08 13:41:38 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 03 15:23:51 2017 +0200"
      },
      "message": "gma broxton: Implement pre-PLL setup for DDI PHYs\n\nSome lane configuration that\u0027s supposed to happen before enabling\nthe display PLL.\n\nChange-Id: I08ec3ac26164061b19d695ab600d6bb9eeadd7ad\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18424\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "f6266004f9c8dcbb7493b409de02048ef209387e",
      "tree": "085df262f70edf1296143f247d2b4e2ee830add4",
      "parents": [
        "408204409b3324ae6ae7043826ee5ab7bb45bb2f"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Fri Feb 03 12:17:28 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 03 15:23:22 2017 +0200"
      },
      "message": "gma broxton: Implement DDI PHY power handling\n\nDDI PHYs is a concept common to current Atom processor series. It\nseems the PHYs are implemented on the same die as the graphics core\nbut still need to be configured separately. Based on the assumption\nthat we start with disabled PHYs and it was always us if they are\nenabled, we only have to do a small share of what Linux\u0027 i915 does.\n\nv2: Wait for GRC done only if we want to copy its results.\n\nChange-Id: I1e59f80daa08dc64b8c3dff34202ace5dd4c5f73\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18422\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "408204409b3324ae6ae7043826ee5ab7bb45bb2f",
      "tree": "771cd2b63dc548d61a0d3a42f7bce72c7ed3acd6",
      "parents": [
        "21da5741378af7c9f8db23b55aa316a905ae9183"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Fri Jan 20 14:00:53 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 03 15:22:31 2017 +0200"
      },
      "message": "gma broxton: Start off with power domains and CDClk\n\nIt\u0027s close to the respective code for Skylake but still different\nenough for a separate implementation. We start with a default CDClk\nof 288MHz which is enough for resolutions up to 2560x1600.\n\nChange-Id: I44364191236f421b2b89c9a019a50713f7c20525\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18243\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    }
  ]
}