)]}' { "log": [ { "commit": "6dc7843082cf50e71001c9b24850bfbc86c3a39e", "tree": "95cf2104a7df44ca0ab46b8b4a0c3be9ccded8f4", "parents": [ "3d7c33f5d24b27b1b140d91af89628ea3caa86ac" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Thu Jun 18 09:34:50 2026 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 17 18:19:31 2026 +0000" }, "message": "gma i945: Add Pineview support\n\nAdd Pineview desktop and mobile variants to the existing i945/Gen3\ncode path. Pineview is close to i945, but Linux\u0027 i915 treats a few\npieces differently and those differences need explicit handling:\n\n- add Pineview/Pineview_M CPU types and PCI IDs 0xa001/0xa011\n- detect Pineview-M as a mobile Gen3 platform so LVDS is exposed\n- decode Pineview GCFGC display clock selections for 133/167/200/\n 267/333/444 MHz CDClk\n- use the mobile/Pineview CLKCFG FSB encoding for HRAW clock\n- keep the separate BAR3 Gen3 GTT layout, but use the i965/G33 style\n PTE encoding for Pineview\u0027s 36-bit DMA addresses\n- add a separate Pineview DPLL calculation/programming path instead of\n widening the i945 PLL ranges; Pineview has a one-hot N encoding in\n the frequency-parameter (FP) register, no M1 divider, M \u003d M2 + 2,\n and P1 at bit 15\n\nThe i945 PLL type ranges and calculation path remain unchanged.\n\nTested with:\n make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/ironlake\n make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/ironlake_edp\n make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/i945\n\nTested with coreboot on Foxconn D41S.\n\nChange-Id: I8bda5d27e1c071bd59bd9a8751dc1ea31b25614f\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/515\nTested-by: Ada SPARK \u003cgnatbot@sourcearcade.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4ba4911b0ccddfcb54a572ebdfb9b9762c7bce4d", "tree": "9bc9dc34e49771b540ea28e2600115f252e4de7a", "parents": [ "4cafa4a4eb95d12f0b18aaa1de5b1527f7a0c484" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Jun 10 16:31:36 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 13 12:27:58 2026 +0000" }, "message": "gma: Make PCI config access mandatory\n\nWe always have access to the PCI device now. So we can drop the old\n`Check_Platform ()` that relied on the MMIO space only. Some paths\nalso get simplified, as we don\u0027t need the `PCI_Usable` flag anymore.\n\nChange-Id: I29f2d79484eae2f84b8547e52869d8f6246024a0\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/537\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "41e8674b7180778ed4beec9fc55c988aef330ebe", "tree": "839a4ffa6f5602f9b2f4a9487f0432cb86ad09c5", "parents": [ "1b99185ac3275f8d231e734a92d4f1e25a2eb829" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Jul 17 17:10:28 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 06 10:28:13 2026 +0000" }, "message": "gma power: Allow to explicitly enable DDI/Aux power\n\nWe used to enable power for DP-aux channels quite implicitly by faking\nconfigs that use a specific port. As Tiger Lake requires us to enable\na DDI port\u0027s power late during the modesetting sequence, we introduce\na new API for such cases, and also use it for the DP-aux case.\n\nTested on HSW, and BXT \u0026 CFL where we enable PW2 explicitly now.\n\nChange-Id: I1fd6348ff4855557166495613c6a181f85a818f4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/461\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "960e239abb429da6f9c6718d12ffd5d649fa9892", "tree": "0d2d212be1aa9e55fe93bcf503fe17048a96b99d", "parents": [ "3c3828add50024e90e57d6fbe0e660d1b66302d9" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Mar 03 19:45:24 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 06 10:23:00 2026 +0000" }, "message": "gma: Add Intel i945 (Gen3) graphics init support\n\nAdd i945G (desktop) and i945GM (mobile) generation support, modeled\nafter the existing G45 generation code with hardware-specific\nadaptations based on the Linux i915 DRM driver and coreboot.\n\nKey hardware differences from G45 (Gen4):\n- GTT on separate PCI BAR3 (not within BAR0)\n- Simple 32-bit GTT PTEs (addr[31:12] | valid[0])\n- No DSPSURF register (uses DSPADDR/DSPLINOFF instead)\n- Gen3 fence registers: 32-bit at split 0x2000/0x3000 addresses\n- Different PLL limits (VCO 1400-2800 MHz, 96 MHz refclk)\n- SDVO multiplier in DPLL register bits[7:4]\n- LVDS restricted to Pipe B (pre-i965 requirement)\n- CDClk: fixed 400 MHz (desktop) or GCFGC-based (mobile)\n- No HDMI/DP, only VGA, LVDS, and SDVO outputs\n- PCI IDs: 0x2772 (I945G), 0x27a2/0x27ae (I945GM)\n\nTESTED with thinkpad x60: LVDS \u0026 VGA works with a linear framebuffer.\n\nChange-Id: Ib67b3d0ee5e06df427869dce4db926ba57a80fd8\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/476\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ] }