)]}'
{
  "log": [
    {
      "commit": "a8254480fa08969d60b67456f299dd263056d6c9",
      "tree": "577d9650c6c4e7772ce013a94b14774752f218e5",
      "parents": [
        "41e8674b7180778ed4beec9fc55c988aef330ebe"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Jul 03 12:23:00 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 06 10:28:13 2026 +0000"
      },
      "message": "gma connectors: Add a Prepare() step\n\nPrepare() will be used to adapt a `Port_Config\u0027 to platform quirks.\nFor instance the FDI usage on Ironlake, USB-C usage on Tiger Lake.\n\nChange-Id: I2fb3ed026077f0371112682b90bea751a28bf994\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/462\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "41e8674b7180778ed4beec9fc55c988aef330ebe",
      "tree": "839a4ffa6f5602f9b2f4a9487f0432cb86ad09c5",
      "parents": [
        "1b99185ac3275f8d231e734a92d4f1e25a2eb829"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Jul 17 17:10:28 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 06 10:28:13 2026 +0000"
      },
      "message": "gma power: Allow to explicitly enable DDI/Aux power\n\nWe used to enable power for DP-aux channels quite implicitly by faking\nconfigs that use a specific port.  As Tiger Lake requires us to enable\na DDI port\u0027s power late during the modesetting sequence,  we introduce\na new API for such cases, and also use it for the DP-aux case.\n\nTested on HSW, and BXT \u0026 CFL where we enable PW2 explicitly now.\n\nChange-Id: I1fd6348ff4855557166495613c6a181f85a818f4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/461\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "960e239abb429da6f9c6718d12ffd5d649fa9892",
      "tree": "0d2d212be1aa9e55fe93bcf503fe17048a96b99d",
      "parents": [
        "3c3828add50024e90e57d6fbe0e660d1b66302d9"
      ],
      "author": {
        "name": "Arthur Heymans",
        "email": "arthur@aheymans.xyz",
        "time": "Tue Mar 03 19:45:24 2026 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 06 10:23:00 2026 +0000"
      },
      "message": "gma: Add Intel i945 (Gen3) graphics init support\n\nAdd i945G (desktop) and i945GM (mobile) generation support, modeled\nafter the existing G45 generation code with hardware-specific\nadaptations based on the Linux i915 DRM driver and coreboot.\n\nKey hardware differences from G45 (Gen4):\n- GTT on separate PCI BAR3 (not within BAR0)\n- Simple 32-bit GTT PTEs (addr[31:12] | valid[0])\n- No DSPSURF register (uses DSPADDR/DSPLINOFF instead)\n- Gen3 fence registers: 32-bit at split 0x2000/0x3000 addresses\n- Different PLL limits (VCO 1400-2800 MHz, 96 MHz refclk)\n- SDVO multiplier in DPLL register bits[7:4]\n- LVDS restricted to Pipe B (pre-i965 requirement)\n- CDClk: fixed 400 MHz (desktop) or GCFGC-based (mobile)\n- No HDMI/DP, only VGA, LVDS, and SDVO outputs\n- PCI IDs: 0x2772 (I945G), 0x27a2/0x27ae (I945GM)\n\nTESTED with thinkpad x60: LVDS \u0026 VGA works with a linear framebuffer.\n\nChange-Id: Ib67b3d0ee5e06df427869dce4db926ba57a80fd8\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/476\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    }
  ]
}